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41. 发明授权

US06593608B1 Magneto resistive storage device having double tunnel junction 有权
标题翻译：具有双隧道结的磁电阻存储装置
公开(公告)号：US06593608B1
公开(公告)日：2003-07-15
申请号：US10098204
申请日：2002-03-15
申请人： Manish Sharma , Lung T. Tran
发明人： Manish Sharma , Lung T. Tran
IPC分类号： H01L31062
CPC分类号： B82Y25/00 , G11C11/15 , G11C11/16 , G11C11/5607 , H01F10/3254 , H01F10/3263
摘要： A magnetic memory device is disclosed that includes first and second soft reference layers, first and second barrier layers, and a sense layer, bound between the first and second barrier layers, which are further bound by the first and second soft reference layers.
摘要翻译：公开了一种磁存储器件，其包括第一和第二软参考层，第一和第二阻挡层以及界定在第一和第二阻挡层之间的感测层，其进一步由第一和第二软参考层限制。

42. 发明授权

US06515896B1 Memory device with short read time 有权
标题翻译：具有短读取时间的存储器件
公开(公告)号：US06515896B1
公开(公告)日：2003-02-04
申请号：US09910823
申请日：2001-07-24
申请人： Lung T. Tran
发明人： Lung T. Tran
IPC分类号： G11C1114
CPC分类号： G11C11/16 , G11C11/15
摘要： The memory device includes a memory array of memory cells, and intersecting word lines and bit lines. At one end of the array, a bank of read/write select switches selectively couples the bit lines to a column write current source, and to a reference potential voltage. A bank of sense amplifier select switches selectively couples the bit lines to a sense amplifier, which is also at the reference potential voltage. Each switch in the bank of sense amplifier select switches may be closed to allow the sense amplifier to sense the binary state of a selected memory cell. The switches in the bank of read/write select switches may each be closed to couple a selected bit line to reference potential voltage. During read operations, the bank of sense amplifier select switches and the bank of read write select switches are operated so that ends of the bit lines are coupled to the reference potential voltage, so that the memory array remains in an equipotential state. Because the memory array remains in the equipotential state, no settling time is required for the memory array due to multiplexing to the sense amplifier. Read operations are therefore faster than in conventional devices.
摘要翻译：存储器件包括存储器单元的存储器阵列，以及相交的字线和位线。在阵列的一端，一组读/写选择开关选择性地将位线耦合到列写入电流源和参考电位电压。读出放大器选择开关组选择性地将位线耦合到也在参考电位电压的读出放大器。读出放大器选择开关组中的每个开关可以闭合，以允许读出放大器感测所选存储单元的二进制状态。读/写选择开关组中的开关可以分别关闭以将所选位线耦合到参考电位电压。在读取操作期间，读出放大器组选择开关，并且操作读取写入选择开关组，使得位线的端部耦合到参考电位电压，使得存储器阵列保持等电位状态。由于存储器阵列保持在等电位状态，由于与读出放大器的多路复用，存储器阵列不需要建立时间。因此，读操作比传统设备更快。

43. 发明授权

US06885573B2 Diode for use in MRAM devices and method of manufacture 有权
标题翻译：用于MRAM器件的二极管及其制造方法
公开(公告)号：US06885573B2
公开(公告)日：2005-04-26
申请号：US10098206
申请日：2002-03-15
申请人： Manish Sharma , Lung T. Tran
发明人： Manish Sharma , Lung T. Tran
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C17/06
CPC分类号： H01L27/224 , G11C11/00 , G11C11/15 , G11C11/16
摘要： A data storage device is disclosed that has a plurality of word lines, a plurality of bit lines, and a resistive crosspoint array of memory cells. Each memory cell is connected to a bit line and connected to an isolation diode that further connects to a respective word line. The isolation diode provides a unidirectional conductive path from the bit line to the word line. Each word line provides a common metal-semiconductor contact with each diode sharing the word line such that each diode has a separate metal contact located between the semiconductor portion of the common metal-semiconductor contact and its respective memory cell.
摘要翻译：公开了一种数据存储装置，其具有多个字线，多个位线和存储器单元的电阻交叉点阵列。每个存储单元连接到位线并连接到进一步连接到相应字线的隔离二极管。隔离二极管提供从位线到字线的单向导电路径。每个字线提供与共享字线的每个二极管共同的金属 - 半导体接触，使得每个二极管具有位于公共金属 - 半导体触点的半导体部分和其相应存储单元之间的单独的金属触点。

44. 发明授权

US06865105B1 Thermal-assisted switching array configuration for MRAM 有权
标题翻译： MRAM热辅助开关阵列配置
公开(公告)号：US06865105B1
公开(公告)日：2005-03-08
申请号：US10668405
申请日：2003-09-22
申请人： Lung T. Tran
发明人： Lung T. Tran
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15
摘要： This invention provides a thermal-assisted switching magnetic memory storage device. In a particular embodiment, a cross-point array of conductive rows and columns is provided with offset tunnel junction magnetic memory cells provided proximate to the intersections between the rows and columns. A looping write conductor is provided close to, but not in electrical contact with each memory cell. The looping write conductor loops across the top and bottom of each memory cell. Each magnetic memory cell provides a magnetic data layer characterized by a material wherein the coercivity is decreased upon an increase in temperature, an intermediate layer, and a reference layer. The magnetic fields provided by the looping write conductor during a write operation are not sufficient to alter the magnetic orientation of an unheated data layer, but may alter the data layer of a memory cell warmed by a bias current tunneling through the memory cell.
摘要翻译：本发明提供一种热辅助切换磁存储器存储装置。在特定实施例中，导电行和列的交叉点阵列设置有靠近行和列之间的交叉点设置的偏移隧道结磁存储单元。环形写导体靠近但不与每个存储单元电接触。循环写入导体环绕每个存储单元的顶部和底部。每个磁存储单元提供一个磁性数据层，其特征在于其中矫顽力在温度升高时降低，中间层和参考层。在写入操作期间由循环写入导体提供的磁场不足以改变未加热的数据层的磁性取向，而是可以改变通过穿过存储器单元的偏置电流加热的存储器单元的数据层。

45. 发明授权

US06826079B2 Method and system for performing equipotential sensing across a memory array to eliminate leakage currents 有权
标题翻译：用于在存储器阵列上执行等电位感测以消除泄漏电流的方法和系统
公开(公告)号：US06826079B2
公开(公告)日：2004-11-30
申请号：US10459437
申请日：2003-06-10
申请人： Lung T. Tran
发明人： Lung T. Tran
IPC分类号： G11C700
CPC分类号： G11C11/16
摘要： A method and system for minimizing a leaked current within an array of memory cells as well as a method and system for differentiating a resistive value within a sensed memory cell during a read operation are disclosed. The memory array includes a plurality of bit lines and word lines that are cross-coupled via a plurality of memory cells. Each memory cell is limited in providing a conductive path in a first direction only by way of a unidirectional element. Such unidirectional elements typically comprise of diodes. The apparatus utilizes the diodes to form a current path from the bit line to the word line having passed through the diode and resistive memory cell. Further, a differential sense amplifier is utilized to differentiate the sensed current during a read operation from a reference value after an equipotential value is placed across the array to limit leakage current from developing within adjoining word and bit lines during a sense operation of a given memory cell.
摘要翻译：公开了一种用于最小化存储器单元阵列内的漏电流的方法和系统，以及用于在读操作期间区分感测存储单元内的电阻值的方法和系统。存储器阵列包括经由多个存储器单元交叉耦合的多个位线和字线。限制每个存储单元仅通过单向元件在第一方向上提供导电路径。这种单向元件通常包括二极管。该装置利用二极管形成从位线到通过二极管和电阻存储单元的字线的电流路径。此外，在给定存储器的感测操作期间，在将等电位值放置在阵列上之后，利用差分读出放大器将读取操作期间的感测电流与参考值区分开来，以限制在相邻字和位线内发生的泄漏电流细胞。

46. 发明授权

US06801451B2 Magnetic memory devices having multiple bits per memory cell 有权
公开(公告)号：US06801451B2
公开(公告)日：2004-10-05
申请号：US10235045
申请日：2002-09-03
申请人： Lung T. Tran , Manish Sharma
发明人： Lung T. Tran , Manish Sharma
IPC分类号： G11C1100
CPC分类号： G11C11/5607
摘要： A memory cell of a data storage device includes serially-connected first and second magnetoresistive devices. The first magnetoresistive device has first and second resistance states. The second magnetoresistive device has third and fourth resistance states. The four resistance states are detectably different.

47. 发明授权

US06778421B2 Memory device array having a pair of magnetic bits sharing a common conductor line 有权
标题翻译：具有共享公共导体线的一对磁性位的存储器件阵列
公开(公告)号：US06778421B2
公开(公告)日：2004-08-17
申请号：US10098903
申请日：2002-03-14
申请人： Lung T. Tran
发明人： Lung T. Tran
IPC分类号： G11C1706
CPC分类号： G11C11/16 , H01L27/224
摘要： A magnetic random access memory (MRAM) device having parallel memory planes is disclosed. Each memory plane includes a first magneto-resistive cross point plane of memory cells, a second magneto-resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a first plurality of bit lines, each of the first plurality of bit lines coupling one or more cells from the first plane to at least one other memory cell in the first plane, a second plurality of bit lines, each of the second plurality of bit lines coupling one or more cells from the second plane to at least one other memory cell in the second plane, and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The device further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.
摘要翻译：公开了一种具有并行存储器平面的磁性随机存取存储器（MRAM）器件。每个存储器平面包括存储器单元的第一磁阻交叉点平面，存储器单元的第二磁阻交叉点平面，在存储器单元的第一和第二平面之间共享的多个导电字线，第一多个位所述第一多个位线中的每一个将所述第一平面中的一个或多个单元耦合到所述第一平面中的至少一个其它存储单元，所述第二多个位线，所述第二多个位线中的每一个耦合一个或多个单元从第二平面到第二平面中的至少一个其它存储单元，以及多个单向元件。此外，一个单向元件将第一存储器单元从第一平面耦合到所选择的字线，并且第一导电方向上的选定位线和第二单向元件将第二单元从第二平面耦合到所选择的字线并选择位线在第二导电方向上。该装置还提供从第一平面中的存储器单元形成到共享相同位线的第二平面中的存储器单元的单向导电路径。

48. 发明授权

US06538917B1 Read methods for magneto-resistive device having soft reference layer 有权
标题翻译：具有软参考层的磁阻器件的读取方法
公开(公告)号：US06538917B1
公开(公告)日：2003-03-25
申请号：US09963851
申请日：2001-09-25
申请人： Lung T. Tran , Manish Sharma
发明人： Lung T. Tran , Manish Sharma
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A magneto-resistive device includes data and reference layers having different coercivities. Each layer has a magnetization that can be oriented in either of two directions. The memory device may be read by temporarily setting the magnetization of the reference layer to a known orientation, and determining a resistance state of the device.
摘要翻译：磁阻装置包括具有不同矫顽力的数据和参考层。每个层具有可以在两个方向中的任一方向上定向的磁化。可以通过将参考层的磁化临时设置为已知取向来读取存储器件，并且确定器件的电阻状态。

49. 发明授权

US06434060B1 Write pulse limiting for worm storage device 有权
标题翻译：为蠕虫存储设备写入脉冲限制
公开(公告)号：US06434060B1
公开(公告)日：2002-08-13
申请号：US09917882
申请日：2001-07-31
申请人： Lung T. Tran , Manish Sharma
发明人： Lung T. Tran , Manish Sharma
IPC分类号： G11C700
CPC分类号： G11C16/3486 , G11C17/16 , G11C17/18
摘要： A method and circuit write a memory cell. The method applies a pulse to a write line connected to the memory cell. The duration of the pulse is not predetermined. The method compares a value on the input side of the cell to a reference value. The method discontinues the pulse on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. The circuit comprises a pulse generator and a comparator. The pulse generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the write line, whereby the pulse is disabled or enabled on the write line depending upon comparator output. A complete memory system comprises an array of memory cells, a write line, and a pulse generator and comparator as described above.
摘要翻译：一种方法和电路写入一个存储单元。该方法向连接到存储单元的写入线施加脉冲。脉冲的持续时间不是预定的。该方法将单元格输入端的值与参考值进行比较。该方法响应于比较步骤中止写入线上的脉冲，优选地，如果写入线上的值超过参考值。电路包括脉冲发生器和比较器。脉冲发生器具有输出和使能输入。输出连接到连接到存储单元的写入线。输出，当使能时，会携带一个脉冲。比较器有两个输入和一个输出。其中一个输入连接到写入线。另一个输入连接到引用。输出连接到写入线，根据比较器输出，脉冲在写入线上被禁止或使能。完整的存储器系统包括如上所述的存储器单元阵列，写入线以及脉冲发生器和比较器。

50. 发明授权

US06434048B1 Pulse train writing of worm storage device 有权
标题翻译：脉冲串写蜗杆存储装置
公开(公告)号：US06434048B1
公开(公告)日：2002-08-13
申请号：US09908901
申请日：2001-07-20
申请人： Lung T. Tran , Manish Sharma
发明人： Lung T. Tran , Manish Sharma
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1006 , G11C7/1078
摘要： A method and circuit write a memory cell. The method applies a pulse train to a write line connected to the memory cell. The number of pulses in the pulse train is not predetermined. The method compares a value on the input side of the cell to a reference value, wherein the input side of the memory cell provides an indication that a writing operation is complete. The method discontinues the pulse train on the write line, in response to the comparing step, preferably if the value on the write line exceeds the reference value. Preferably, the pulses are short in width and large in magnitude. The method may optionally count the number of pulses in the pulse train, and discontinue the pulse train on the write line and/or declare the cell as unusable if the number of pulses exceeds a predetermined maximum. The circuit comprises a pulse train generator and a comparator. The pulse train generator has an output and an enable input. The output is connected to a write line connected to the memory cell. The output, when enabled, carries a pulse train. The comparator has two inputs and an output. One of the inputs is connected to the write line. The other of the inputs is connected to a reference. The output is connected to the enable input of the pulse train generator, whereby the pulse train generator is disabled or enabled depending upon the comparator output. Optionally, the circuit further comprises a counter that counts pulses and disables the pulse train generator after a predetermined maximum number of pulses. A complete memory system comprises an array of memory cells, a write line, and a pulse train generator and comparator as described above.
摘要翻译：一种方法和电路写入一个存储单元。该方法将脉冲串应用于连接到存储单元的写入线。脉冲串中的脉冲数不是预定的。该方法将小区的输入侧的值与参考值进行比较，其中存储单元的输入侧提供写入操作完成的指示。该方法响应于比较步骤中止写入线上的脉冲序列，优选地，如果写入线上的值超过参考值。优选地，脉冲的宽度较短，而且幅度较大。该方法可以可选地计数脉冲串中的脉冲数，并且如果脉冲数超过预定最大值，则在写入线上中止脉冲序列和/或将单元声明为不可用。电路包括脉冲串发生器和比较器。脉冲串发生器具有输出和使能输入。输出连接到连接到存储单元的写入线。输出，当使能时，携带脉冲串。比较器有两个输入和一个输出。其中一个输入连接到写入线。另一个输入连接到引用。输出连接到脉冲串发生器的使能输入端，根据比较器输出，脉冲串发生器被禁止或使能。可选地，电路还包括计数器，其计数脉冲并且在预定的最大脉冲数之后禁用脉冲序列发生器。完整的存储器系统包括如上所述的存储器单元阵列，写入线以及脉冲序列发生器和比较器。

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