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41. 发明申请

US20050255643A1 Method of forming fin field effect transistor using damascene process 有权
标题翻译：使用镶嵌工艺形成翅片场效应晶体管的方法
公开(公告)号：US20050255643A1
公开(公告)日：2005-11-17
申请号：US11112818
申请日：2005-04-21
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L29/786
CPC分类号： H01L29/7851 , H01L21/26586 , H01L29/66818
摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.
摘要翻译：提供了一种使用镶嵌工艺形成鳍式晶体管的方法。填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

42. 发明授权

US07514325B2 Fin-FET having GAA structure and methods of fabricating the same 有权
标题翻译：具有GAA结构的Fin-FET及其制造方法
公开(公告)号：US07514325B2
公开(公告)日：2009-04-07
申请号：US11505936
申请日：2006-08-18
申请人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
发明人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795
摘要： Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.
摘要翻译：本发明的示例性实施例涉及一种半导体器件及其制造方法。本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管（Fin-FET）及其制造方法。提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全（GAA）结构的鳍FET。具有GAA结构的Fin-FET包括具有主体，一对支撑柱和鳍的半导体衬底。一对支柱可能从身体突出。翅片可以与主体间隔开，并且可以具有连接到一对支撑柱并由其支撑的端部。栅电极可围绕半导体衬底的鳍的至少一部分。栅电极可以与半导体衬底绝缘。栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。

43. 发明授权

US07329580B2 Method of fabricating a semiconductor device having self-aligned floating gate and related device 有权
标题翻译：制造具有自对准浮动栅极和相关器件的半导体器件的方法
公开(公告)号：US07329580B2
公开(公告)日：2008-02-12
申请号：US11425205
申请日：2006-06-20
申请人： Byung-Yong Choi , Choong-Ho Lee , Tae-Yong Kim , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Tae-Yong Kim , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.
摘要翻译：提供了诸如具有自对准浮动栅极的闪速存储器件及其制造方法的半导体器件。该器件的一个实施例包括在半导体衬底中形成限定翅片体的隔离层。翅片本体具有突出在隔离层上方的部分。在隔离层上形成牺牲图案。牺牲图案具有与翅片体的突出部分自对准的开口。突出的翅片体露出开口。形成绝缘浮栅图形以填充开口。然后去除牺牲图案。形成覆盖浮栅图案的栅极间介电层。在栅极间电介质层上形成控制栅极导电层。对控制栅极导电层，栅极间电介质层和浮置栅极图案进行图案化以形成跨越鳍体的控制栅电极以及插在控制栅电极和鳍体之间的绝缘浮栅。

44. 发明申请

US20050239252A1 Methods of forming integrated circuit devices having field effect transistors of different types in different device regions 有权
标题翻译：在不同的器件区域形成具有不同类型的场效应晶体管的集成电路器件的方法
公开(公告)号：US20050239252A1
公开(公告)日：2005-10-27
申请号：US11110167
申请日：2005-04-20
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8232 , H01L21/8234 , H01L21/8239 , H01L29/786 , H01L31/0328
CPC分类号： H01L21/823412 , H01L21/823437 , H01L21/823456 , H01L21/823462 , H01L27/1052 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect transistor in a peripheral circuit portion of the semiconductor substrate. The non-planar field-effect transistor may be selected from the group of a FinFET and a recessed gate FET. Dopants may be implanted into a channel region of the non-planar field-effect transistor, and a cell protection layer may be formed on the non-planar field-effect transistor. Then, dopants may be selectively implanted into a channel region of the planar field-effect transistor using the cell protection layer as a mask to block implanting of the dopants into the channel region of the non-planar field-effect transistor.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的单元阵列部分中形成非平面场效应晶体管，并在半导体衬底的外围电路部分中形成平面场效应晶体管。非平面场效应晶体管可以选自FinFET和凹入栅极FET。可以将掺杂剂注入到非平面场效应晶体管的沟道区域中，并且可以在非平面场效应晶体管上形成电池保护层。然后，可以使用电池保护层作为掩模将掺杂剂选择性地注入到平面场效应晶体管的沟道区域中，以阻止掺杂剂注入到非平面场效应晶体管的沟道区域中。

45. 发明授权

US07419859B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07419859B2
公开(公告)日：2008-09-02
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

46. 发明申请

US20070145431A1 Fin-FET having GAA structure and methods of fabricating the same 有权
标题翻译：具有GAA结构的Fin-FET及其制造方法
公开(公告)号：US20070145431A1
公开(公告)日：2007-06-28
申请号：US11505936
申请日：2006-08-18
申请人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
发明人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795
摘要： Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.
摘要翻译：本发明的示例性实施例涉及一种半导体器件及其制造方法。本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管（Fin-FET）及其制造方法。提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全（GAA）结构的鳍FET。具有GAA结构的Fin-FET包括具有主体，一对支撑柱和鳍的半导体衬底。一对支柱可能从身体突出。翅片可以与主体间隔开，并且可以具有连接到一对支撑柱并由其支撑的端部。栅电极可围绕半导体衬底的鳍的至少一部分。栅电极可以与半导体衬底绝缘。栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。

47. 发明申请

US20070048934A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US20070048934A1
公开(公告)日：2007-03-01
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

48. 发明申请

US20080293215A1 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
公开(公告)号：US20080293215A1
公开(公告)日：2008-11-27
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

49. 发明申请

US20070205459A1 Nonvolatile memory devices and methods of forming the same 审中-公开
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20070205459A1
公开(公告)日：2007-09-06
申请号：US11653359
申请日：2007-01-16
申请人： Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee , Jong-Jin Lee , Jeong-Dong Choe
发明人： Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee , Jong-Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7854 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a semiconductor pin including a first semiconductor pattern, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern, disposed between the first semiconductor pattern and the second semiconductor pattern, connecting the first semiconductor pattern and the second semiconductor pattern, a charge storage layer on the second semiconductor pattern with a tunneling insulation layer interposed therebetween, and a gate electrode on the charge storage layer with a blocking insulation layer interposed therebetween, wherein a width of the second semiconductor pattern is greater than a width of the third semiconductor pattern.
摘要翻译：非易失性存储器件包括：半导体引脚，包括第一半导体图案，第一半导体图案上的第二半导体图案和设置在第一半导体图案和第二半导体图案之间的第三半导体图案，将第一半导体图案和第二半导体图案半导体图案，在第二半导体图案上的电荷存储层，其间插入有隧道绝缘层，以及在电荷存储层上的栅电极，其间插入有阻挡绝缘层，其中第二半导体图案的宽度大于宽度的第三半导体图案。

50. 发明申请

US20070090449A1 Non-volatile memory devices and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20070090449A1
公开(公告)日：2007-04-26
申请号：US11580086
申请日：2006-10-13
申请人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
摘要翻译：提供了一种非易失性存储器件及其形成方法。非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

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