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41. 发明申请

US20120020156A1 METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES PERFORMING THE METHOD 有权
标题翻译：编程非易失性存储器件的方法及其方法
公开(公告)号：US20120020156A1
公开(公告)日：2012-01-26
申请号：US13190913
申请日：2011-07-26
申请人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
发明人： Seong Hyeog Choi , Hong Rak Son , Jun Jin Kong , Yong June Kim
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10
摘要： A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.
摘要翻译：一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

42. 发明授权

US08799593B2 Flash memory devices, data randomizing methods of the same, memory systems including the same 有权
标题翻译：闪存设备，数据随机化方法相同，内存系统包括相同
公开(公告)号：US08799593B2
公开(公告)日：2014-08-05
申请号：US13237350
申请日：2011-09-20
申请人： Jung Soo Chung , Yong June Kim , Hong Rak Son , Jun Jin Kong
发明人： Jung Soo Chung , Yong June Kim , Hong Rak Son , Jun Jin Kong
IPC分类号： G06F13/28 , G06F12/02
CPC分类号： G06F12/0246
摘要： Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.
摘要翻译：公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列，以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

43. 发明申请

US20120166708A1 FLASH MEMORY DEVICES, DATA RANDOMIZING METHODS OF THE SAME, MEMORY SYSTEMS INCLUDING THE SAME 有权
标题翻译：闪存存储器件，其数据随机化方法，包括其的存储器系统
公开(公告)号：US20120166708A1
公开(公告)日：2012-06-28
申请号：US13237350
申请日：2011-09-20
申请人： Jung Soo Chung , Yong June Kim , Hong Rak Son , Jun Jin Kong
发明人： Jung Soo Chung , Yong June Kim , Hong Rak Son , Jun Jin Kong
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer.
摘要翻译：公开了一种闪速存储器件，其包括被配置为存储数据的存储器单元阵列，被配置为生成随机序列的随机器，以使用与要在存储器单元阵列中编程的数据相关联的存储器参数中的至少一个来交织随机序列，以及控制逻辑电路，被配置为将所述存储器参数提供给所述随机发生器并且控制所述随机发生器。

44. 发明申请

US20100002506A1 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US20100002506A1
公开(公告)日：2010-01-07
申请号：US12318560
申请日：2008-12-31
申请人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Yong June Kim
发明人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Yong June Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C29/00 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括：多级单元阵列，其包括多个多电平单元; 编程单元，其对所述多个多电平单元中的第一数据页进行编程，并从所述第一数据页被编程的所述多个多电平单元中编程多电平单元中的第二数据页; 误差分析单元，其基于读取电压电平分析与所述第一数据页相对应的读取错误信息，以基于所分析的读取错误信息来确定是否校正读取错误; 以及控制器，其根据确定结果调整第一数据页的读取电压电平。通过这种方式，可以在读取和/或编程数据页时减少错误发生。

45. 发明授权

US09495518B2 Method of reliably reading data stored in multi-level cell (MLC) non-volatile memory 有权
标题翻译：可靠地读取存储在多级单元（MLC）非易失性存储器中的数据的方法
公开(公告)号：US09495518B2
公开(公告)日：2016-11-15
申请号：US13407333
申请日：2012-02-28
申请人： Yong June Kim , Hong Rak Son , Jae Hong Kim , Sang Yong Yoon , Ki Jun Lee , Jung Soo Chung , Seong Hyeog Choi
发明人： Yong June Kim , Hong Rak Son , Jae Hong Kim , Sang Yong Yoon , Ki Jun Lee , Jung Soo Chung , Seong Hyeog Choi
IPC分类号： G06F12/00 , G06F21/00 , G06F12/14 , G11C11/00 , G11C11/56 , G11C16/26 , G11C16/34 , G06F11/10
CPC分类号： G06F21/00 , G06F11/1012 , G06F11/108 , G06F12/00 , G06F12/14 , G11C11/00 , G11C11/5642 , G11C16/26 , G11C16/3418
摘要： An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.
摘要翻译：一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。使用软判决数据，硬判决数据被解码。

46. 发明申请

US20090296486A1 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US20090296486A1
公开(公告)日：2009-12-03
申请号：US12382351
申请日：2009-03-13
申请人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
发明人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.
摘要翻译：提供存储器件和/或存储器编程方法。存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。由此，可以减小存储单元的阈值电压分布的宽度。

47. 发明授权

US08432735B2 Memory system and related method of programming 有权
标题翻译：内存系统和相关的编程方法
公开(公告)号：US08432735B2
公开(公告)日：2013-04-30
申请号：US12832220
申请日：2010-07-08
申请人： Yong June Kim , Jae hong Kim , Ki jun Lee
发明人： Yong June Kim , Jae hong Kim , Ki jun Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C7/1012 , G11C11/5642 , G11C2211/5647
摘要： A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.
摘要翻译：一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器设备。每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据。连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

48. 发明授权

US08059467B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US08059467B2
公开(公告)日：2011-11-15
申请号：US12382351
申请日：2009-03-13
申请人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
发明人： Jae Hong Kim , Kyoung Lae Cho , Yong June Kim , Dong Hyuk Chae
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C2211/5621
摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.
摘要翻译：提供存储器件和/或存储器编程方法。存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。由此，可以减小存储单元的阈值电压分布的宽度。

49. 发明申请

US20110032759A1 MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING 有权
标题翻译：记忆系统及相关编程方法
公开(公告)号：US20110032759A1
公开(公告)日：2011-02-10
申请号：US12832220
申请日：2010-07-08
申请人： Yong June Kim , Jae hong Kim , Ki Jun Lee
发明人： Yong June Kim , Jae hong Kim , Ki Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1012 , G11C11/5642 , G11C2211/5647
摘要： A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.
摘要翻译：一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器设备。每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据。连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

50. 发明授权

US07924624B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US07924624B2
公开(公告)日：2011-04-12
申请号：US12385705
申请日：2009-04-16
申请人： Jae Hong Kim , Kyoung Lae Cho , Dong Hyuk Chae , Yong June Kim
发明人： Jae Hong Kim , Kyoung Lae Cho , Dong Hyuk Chae , Yong June Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage.
摘要翻译：提供的是存储器件和存储器编程方法。存储器设备可以包括：包括多个存储器单元的多位单元阵列; 提取每个存储单元的状态信息的控制器，将多个存储器单元划分成第一组和第二组，将第一验证电压分配给第一组的存储单元，并将第二验证电压分配给存储单元第二组以及编程单元，其改变第一组的每个存储单元的阈值电压，直到第一组的每个存储单元的阈值电压大于或等于第一验证电压，并且改变每个存储单元的阈值电压直到第二组的每个存储单元的阈值电压大于或等于第二验证电压。

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