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41. 发明申请

US20160328290A1 ERROR VECTOR READOUT FROM A MEMORY DEVICE 有权
公开(公告)号：US20160328290A1
公开(公告)日：2016-11-10
申请号：US14705115
申请日：2015-05-06
申请人： International Business Machines Corporation
发明人： Michael B. Healy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F3/0673 , G06F3/0619 , G06F3/064 , G06F11/08 , G06F11/1032 , G06F11/1048 , G06F11/106 , G06F11/1072 , G06F11/1076 , G11C7/1006 , G11C7/1051 , G11C29/52 , G11C2029/0411
摘要： A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ECC) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ECC) bits and output the raw data and the ECC bits corresponding with memory addresses specified in the read command, and an ECC decoder to output an error vector associated with the memory addresses based on the raw data and the ECC bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses. The system also includes a multiplexer (MUX) to output the error vector based on a selection indicated in the read command.

42. 发明授权

US09389972B2 Data retrieval from stacked computer memory 有权
标题翻译：从堆叠的计算机内存中检索数据
公开(公告)号：US09389972B2
公开(公告)日：2016-07-12
申请号：US14276046
申请日：2014-05-13
申请人： International Business Machines Corporation
发明人： Saurabh Chadha , Hillery C. Hunter , Kyu-hyoun Kim , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G06F11/00 , G06F11/20 , G06F11/14
CPC分类号： G06F11/2094 , G06F11/1048 , G06F11/14 , G06F11/1435 , G06F11/1469 , G06F11/20 , G06F11/2017 , G06F11/2028 , G06F11/2069 , G06F2201/84
摘要： Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.
摘要翻译：响应于识别堆叠的存储器件中的问题，从具有多个从存储器芯片的堆叠存储器件检索数据。该问题被确定为与堆叠存储器件中的主驱动器模块相关联。作为响应，主驱动器模块被禁用并且启用紧急驱动器模块。使用复用单元来选择多个从存储器芯片中的每一个，以使用紧急驱动器模块来检索数据。

43. 发明授权

US09298395B2 Memory system connector 有权
标题翻译：内存系统连接器
公开(公告)号：US09298395B2
公开(公告)日：2016-03-29
申请号：US13657058
申请日：2012-10-22
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Shawn A. Hall , Hillery C. Hunter , Douglas J. Joseph , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Todd E. Takken
IPC分类号： G06F3/06 , H05K7/02 , G06F1/20 , G06F1/32
CPC分类号： G06F3/0671 , G06F1/20 , G06F1/3275 , Y02D10/14
摘要： According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
摘要翻译：根据一个实施例，存储器系统包括电路卡和电路卡上的可分离区域阵列连接器。该系统还包括位于电路卡上的存储器件，其中存储器件被配置为经由区域阵列连接器与计算机系统的主处理器进行通信。

44. 发明申请

US20160027494A1 PRIORITIZING REFRESHES IN A MEMORY DEVICE 有权
标题翻译：在存储设备中优先刷新
公开(公告)号：US20160027494A1
公开(公告)日：2016-01-28
申请号：US14878174
申请日：2015-10-08
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Joab D. Henderson , Kyu-hyoun Kim , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G11C11/406 , G11C11/4076
CPC分类号： G11C11/406 , G11C7/24 , G11C11/403 , G11C11/40603 , G11C11/4076
摘要： A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.
摘要翻译：一种用于在预定刷新之前刷新存储器设备的行的方法和装置。存储器阵列可以包括多个存储器单元。存储器阵列可以被配置为在第一刷新时间间隔被刷新。存储器件还可以包括中间刷新电路。中间刷新电路可以被配置为响应于检测到触发事件来检测触发事件并请求针对存储器阵列的刷新。

45. 发明申请

US20150347036A1 DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING 有权
标题翻译： DRAM控制器，用于不同的刷新操作时序
公开(公告)号：US20150347036A1
公开(公告)日：2015-12-03
申请号：US14823094
申请日：2015-08-11
申请人： International Business Machines Corporation
发明人： Hillery C. Hunter , Kyu-hyoun Kim , Janani Mukundan
IPC分类号： G06F3/06 , G11C11/4076 , G11C11/406
CPC分类号： G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G11C11/40607 , G11C11/40611 , G11C11/4076 , G11C2211/4061
摘要： A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.
摘要翻译：公开了一种在DRAM存储器系统中选择DRAM刷新定时的方法。该方法可以包括使用第一DRAM刷新定时运行第一数量的刷新间隔的工作负载，并且对第一次刷新间隔进行第一工作负载吞吐量测量。该方法还可以包括使用第二DRAM刷新定时对第二数量的刷新间隔运行工作负荷，并且对第二数量的刷新间隔进行第二工作负载吞吐量测量。该方法还可以包括：决定第一吞吐量测量是否大于第二吞吐量测量，然后选择第一DRAM刷新定时作为所选DRAM刷新定时，或者决定第二吞吐量测量是否大于第一吞吐量测量值，则选择第二DRAM刷新定时作为所选择的DRAM刷新定时。

46. 发明授权

US09196347B2 DRAM controller for variable refresh operation timing 有权
标题翻译： DRAM控制器，用于可变刷新操作时序
公开(公告)号：US09196347B2
公开(公告)日：2015-11-24
申请号：US13827691
申请日：2013-03-14
申请人： International Business Machines Corporation
发明人： Hillery C. Hunter , Kyu-hyoun Kim , Janani Mukundan
IPC分类号： G11C11/406 , G06F13/16
CPC分类号： G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F13/1636 , G11C11/40607 , G11C11/40611 , G11C11/4076 , G11C2211/4061
摘要： A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.
摘要翻译：公开了一种在DRAM存储器系统中选择DRAM刷新定时的方法。该方法可以包括使用第一DRAM刷新定时运行第一数量的刷新间隔的工作负载，并且对第一次刷新间隔进行第一工作负载吞吐量测量。该方法还可以包括使用第二DRAM刷新定时对第二数量的刷新间隔运行工作负荷，并且对第二数量的刷新间隔进行第二工作负载吞吐量测量。该方法还可以包括：决定第一吞吐量测量是否大于第二吞吐量测量，然后选择第一DRAM刷新定时作为所选DRAM刷新定时，或者决定第二吞吐量测量是否大于第一吞吐量测量值，则选择第二DRAM刷新定时作为所选择的DRAM刷新定时。

47. 发明申请

US20150331768A1 DATA RETRIEVAL FROM STACKED COMPUTER MEMORY 有权
公开(公告)号：US20150331768A1
公开(公告)日：2015-11-19
申请号：US14462602
申请日：2014-08-19
申请人： International Business Machines Corporation
发明人： Saurabh Chadha , Hillery C. Hunter , Kyu-hyoun Kim , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G06F11/20 , G06F11/14
CPC分类号： G06F11/2094 , G06F11/1048 , G06F11/14 , G06F11/1435 , G06F11/1469 , G06F11/20 , G06F11/2017 , G06F11/2028 , G06F11/2069 , G06F2201/84
摘要： Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

48. 发明申请

US20150331764A1 DATA RETRIEVAL FROM STACKED COMPUTER MEMORY 有权
标题翻译：堆叠计算机内存的数据检索
公开(公告)号：US20150331764A1
公开(公告)日：2015-11-19
申请号：US14276046
申请日：2014-05-13
申请人： International Business Machines Corporation
发明人： Saurabh Chadha , Hillery C. Hunter , Kyu-hyoun Kim , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G06F11/20 , G06F11/14
CPC分类号： G06F11/2094 , G06F11/1048 , G06F11/14 , G06F11/1435 , G06F11/1469 , G06F11/20 , G06F11/2017 , G06F11/2028 , G06F11/2069 , G06F2201/84
摘要： Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.
摘要翻译：响应于识别堆叠的存储器件中的问题，从具有多个从存储器芯片的堆叠存储器件检索数据。该问题被确定为与堆叠存储器件中的主驱动器模块相关联。作为响应，主驱动器模块被禁用并且启用紧急驱动器模块。使用复用单元来选择多个从存储器芯片中的每一个，以使用紧急驱动器模块来检索数据。

49. 发明授权

US09189327B2 Error-correcting code distribution for memory systems 有权
标题翻译：内存系统的错误纠正代码分配
公开(公告)号：US09189327B2
公开(公告)日：2015-11-17
申请号：US14084043
申请日：2013-11-19
申请人： International Business Machines Corporation
发明人： Paul W. Coteus , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Kenneth L. Wright
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1012 , G06F11/108 , G06F2211/109
摘要： According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system.
摘要翻译：根据一个实施例，存储器系统包括多个存储器件和可操作地耦合到存储器件的存储器控制器。存储器控制器被配置为将写入数据分割成多个数据块，其中每个数据块与存储器件之一相关联。存储器控制器还被配置为生成对应于每个数据块的本地纠错码（ECC）的实例，并且将每个数据块与本地ECC的对应实例合并，以形成每个存储器设备的编码数据块。另外，存储器控制器被配置为将每个编码的数据块写入存储器件，使得每个存储器件将数据块中的一个与本地ECC的对应实例一起存储。全局ECC的全局ECC和本地ECC也可以包含在内存系统中。

50. 发明授权

US09064602B2 Implementing memory device with sub-bank architecture 有权
标题翻译：实现具有子银行架构的存储器件
公开(公告)号：US09064602B2
公开(公告)日：2015-06-23
申请号：US14060665
申请日：2013-10-23
申请人： International Business Machines Corporation
发明人： Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule
IPC分类号： G11C8/00 , G11C11/408
CPC分类号： G11C11/408 , G11C11/4087 , G11C11/4097
摘要： A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
摘要翻译：提供了一种用于在计算机系统中实现具有子银行架构的存储器件的方法，系统和存储器控制器。阵列被划分为具有奇数位线和偶数位线的子块。子块与行放大器交替; 其中一行读出放大器仅连接到奇数位线，而下一行读出放大器仅连接到偶数位线。允许一个子块的多个字线同时处于活动状态，其中第一个活动字线将选择连接到偶数位线的存储单元，而第二个活动字线将选择连接到奇数位线的存储单元。

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