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41. 发明申请

WO2019125456A1 QUANTUM DOT DEVICES 审中-公开
公开(公告)号：WO2019125456A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/067842
申请日：2017-12-21
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , THOMAS, Nicole K. , GEORGE, Hubert C. , ROBERTS, Jeanette M. , AMIN, Payam , YOSCOVITS, Zachary R. , CAUDILLO, Roman , CLARKE, James S.
IPC分类号： H01L29/778 , H01L29/66
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

42. 发明申请

WO2019004990A1 QUANTUM DOT DEVICES 审中-公开
公开(公告)号：WO2019004990A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/039166
申请日：2017-06-25
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , THOMAS, Nicole K. , GEORGE, Hubert C. , ROBERTS, Jeanette M. , AMIN, Payam , YOSCOVITS, Zachary R. , CAUDILLO, Roman , CLARKE, James S.
IPC分类号： H01L29/12 , H01L29/66 , H01L29/08 , H01L29/417
摘要： Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of transistors above the array of quantum dot gate electrodes, wherein the array of quantum dot gate electrodes and the array of transistors are each arranged in a grid.

43. 发明申请

WO2018063168A1 ON-CHIP FREQUENCY TUNING OF RESONATOR STRUCTURES IN QUANTUM CIRCUITS 审中-公开
标题翻译：量子电路中谐振器结构的片内频率调谐
公开(公告)号：WO2018063168A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054039
申请日：2016-09-28
申请人： INTEL CORPORATION
发明人： THOMAS, Nicole K. , CLARKE, James S. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , GEORGE, Hubert C.
IPC分类号： G06N99/00 , B82Y10/00
CPC分类号： G06N10/00 , B82Y10/00 , B82Y30/00
摘要： Embodiments of the present disclosure provide a quantum device that includes qubits, at least one resonator, and a resonator tuning assembly, all housed on a single substrate or a single die. By implementing a resonator tuning assembly on the same die as the qubits and its resonator(s), the resonant frequency of the resonator can be controlled on-chip. In this manner, the resonant frequency can be fine-tuned to compensate for manufacturing variations or can be changed for any other purposes, as needed. Integration of means for varying the resonator frequency with the resonator and the qubits can greatly reduce complexity and lower the cost of quantum computing devices and provide an approach that can be efficiently used in large-scale manufacturing. Methods for fabricating such quantum devices are also disclosed.
摘要翻译：本公开的实施例提供了一种量子器件，其包括全部容纳在单个衬底或单个管芯上的量子位，至少一个谐振器和谐振器调谐组件。通过在与量子位及其谐振器相同的管芯上实施谐振器调谐组件，可以在芯片上控制谐振器的谐振频率。以这种方式，谐振频率可以被微调以补偿制造变化，或者可以根据需要被改变用于任何其它目的。利用谐振器和量子位改变谐振器频率的手段的集成可以大大降低复杂性并降低量子计算设备的成本，并提供可以有效用于大规模制造的方法。还公开了制造这种量子器件的方法。

44. 发明申请

WO2018057016A1 QUBIT-DETECTOR DIE ASSEMBLIES 审中-公开
标题翻译： QUBIT-DETECTOR DIE组件
公开(公告)号：WO2018057016A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053607
申请日：2016-09-24
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , THOMAS, Nicole K. , GEORGE, Hubert C. , CLARKE, James S.
IPC分类号： H01L25/07 , H01L25/18 , H01L29/775 , H01L29/12 , H01L29/66
摘要： Disclosed herein are qubit-detector die assemblies, as well as related computing devices and methods. In some embodiments, a die assembly may include: a first die having a first face and an opposing second face, wherein a plurality of active qubit devices are disposed at the first face of the first die; and a second die, mechanically coupled to the first die, having a first face and an opposing second face, wherein a plurality of quantum state detector devices are disposed at the first face of the second die; wherein the first faces of the first and second dies face each other.
摘要翻译：本文公开了量子检测器管芯组件以及相关的计算装置和方法。在一些实施例中，模组件可以包括：具有第一面和相对的第二面的第一模具，其中多个有源量子位器件设置在第一裸片的第一面处; 以及与第一裸片机械耦合的第二裸片，其具有第一面和相对的第二面，其中多个量子状态检测器装置设置在第二裸片的第一面处; 其中第一和第二模具的第一面彼此面对。

45. 发明申请

WO2018044267A1 QUANTUM DOT DEVICES 审中-公开
标题翻译：量子点设备
公开(公告)号：WO2018044267A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/049368
申请日：2016-08-30
申请人： INTEL CORPORATION
发明人： GEORGE, Hubert C. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , CLARKE, James S. , KEYS, Patrick H.
IPC分类号： H01L29/66 , H01L29/12
CPC分类号： H01L29/82 , B82Y10/00 , H01L29/0673 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66977 , H01L29/7613 , H01L29/7781 , H01L29/7782
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material disposed above the quantum well stack, wherein the insulating material includes a trench extending toward the quantum well stack; first and second gates disposed at least partially in the trench; spacers disposed on sides of the first and second gates in the trench, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate; and a third gate disposed at least partially in the trench between the first and second gates and extending between the first and second spacers.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠; 设置在所述量子阱堆叠上方的绝缘材料，其中所述绝缘材料包括朝向所述量子阱堆叠延伸的沟槽; 第一和第二栅极，至少部分地设置在沟槽中; 其中第一间隔物设置在第一栅极的靠近第二栅极的一侧上，并且与第一间隔物物理分离的第二间隔物设置在第一栅极的一侧上第二门的靠近第一门的位置; 以及第三栅极，其至少部分地设置在第一和第二栅极之间的沟槽中并且在第一和第二间隔器之间延伸。

46. 发明申请

WO2018004634A1 FLUX BIAS LINES BELOW QUBIT PLANE 审中-公开
标题翻译： FLUX BIAS LINES低于QUBIT PLANE
公开(公告)号：WO2018004634A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040601
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , YOSCOVITS, Zachary R. , CLARKE, James S. , MICHALAK, David J.
IPC分类号： H01L29/66 , H01L29/12
CPC分类号： G06N10/00 , G01R33/035 , G01R33/0354 , H01L39/223 , H01L39/2493
摘要： Described herein are structures that include flux bias lines for controlling frequencies of qubits in quantum circuits. An exemplary structure includes a substrate, a qubit provided over a surface of the substrate, and a flux bias line provided below the surface of the substrate and configured to control the frequency of the qubit via a magnetic field generated as a result of a current flowing through the flux bias line. Methods for fabricating such structures are disclosed as well.
摘要翻译：这里描述的是包括用于控制量子电路中的量子位的频率的通量偏置线的结构。示例性结构包括衬底，设置在衬底的表面上的量子位以及设置在衬底的表面下方的通量偏置线，并且被配置为经由作为电流流动的结果而产生的磁场来控制量子位的频率通过通量偏置线。也公开了制造这种结构的方法。

47. 发明申请

WO2017217959A1 SUSPENDED JOSEPHSON JUNCTIONS 审中-公开
标题翻译：暂停约瑟夫森结
公开(公告)号：WO2017217959A1
公开(公告)日：2017-12-21
申请号：PCT/US2016/037133
申请日：2016-06-13
申请人： INTEL CORPORATION
发明人： YOSCOVITS, Zachary R. , MICHALAK, David J. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi , CLARKE, James S.
IPC分类号： H01L39/02 , H01L39/12 , H01L39/24
摘要： Described herein are structures that include Josephson Junctions to be used in superconducting qubits of quantum circuits disposed on a substrate. In one aspect of the present disclosure, at least a part of a Josephson Junction of a superconducting qubit is suspended over a substrate, forming a gap between at least the portion of the Josephson Junction and the substrate. Moving at least a portion of the Josephson Junction further away from the substrate by suspending at least a part of the Junction over the substrate allows reducing spurious two-level systems present in the vicinity of the Junction, which, in turn, improves on the qubit decoherence problem. Methods for fabricating such structures are disclosed as well.
摘要翻译：这里描述的是包括用于设置在衬底上的量子电路的超导量子位中的约瑟夫森结的结构。在本公开的一个方面中，超导量子位的约瑟夫逊结的至少一部分悬挂在衬底上，在约瑟夫森结的至少一部分与衬底之间形成间隙。通过在基板上悬挂至少一部分结，使得至少一部分约瑟夫森结更远离基板允许减少存在于结的附近的寄生二能级系统，这进而改善了量子位退相干问题。也公开了制造这种结构的方法。

48. 发明申请

WO2017213659A1 QUANTUM DOT DEVICES WITH GATE INTERFACE MATERIALS 审中-公开
标题翻译：具有栅极界面材料的量子点器件
公开(公告)号：WO2017213659A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036829
申请日：2016-06-10
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , LE, Van H. , ROBERTS, Jeanette M. , MICHALAK, David J. , CLARKE, James S. , YOSCOVITS, Zachary R.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/40 , H01L29/12
摘要： Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.
摘要翻译：本文公开了具有栅极界面材料的量子点器件以及相关的计算装置和方法。例如，量子点器件可以包括量子阱堆叠，栅极界面材料和高k栅极电介质。栅极界面材料可以设置在高k栅极电介质和量子阱堆叠之间。

49. 发明申请

WO2017213658A1 GATE PATTERNING FOR QUANTUM DOT DEVICES 审中-公开
标题翻译：量子点装置的栅极图案化
公开(公告)号：WO2017213658A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036828
申请日：2016-06-10
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S.
IPC分类号： H01L29/778 , H01L29/12 , H01L29/66 , H01L29/80
CPC分类号： H01L29/7782 , B82Y10/00 , B82Y40/00 , G06N10/00 , H01L21/0228 , H01L21/0273 , H01L21/28194 , H01L21/3212 , H01L21/32139 , H01L29/0673 , H01L29/1037 , H01L29/127 , H01L29/165 , H01L29/401 , H01L29/423 , H01L29/42356 , H01L29/42364 , H01L29/42372 , H01L29/42376 , H01L29/437 , H01L29/495 , H01L29/4966 , H01L29/66431 , H01L29/66484 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66977 , H01L29/7613 , H01L29/7781 , H03K17/687 , H03K2017/6878
摘要： Disclosed herein are quantum dot devices with patterned gates, as well as related computing devices and methods. For example, a quantum dot device may include gates disposed on a quantum well stack. In some embodiments, the gates may include a first gate with a first length; two second gates with second lengths arranged such that the first gate is disposed between the second gates; and two third gates with third lengths arranged such that the second gates are disposed between the third gates; and the first, second, and third lengths may all be different. In some embodiments, the gates may include a first set of gates alternatingly arranged with a second set of gates, spacers may be disposed between gates of the first set and gates of the second set, and gates in the first or second set may include a gate dielectric having a U-shaped cross-section.
摘要翻译：本文公开了具有图案化栅极的量子点器件以及相关的计算装置和方法。例如，量子点器件可以包括设置在量子阱堆叠上的栅极。在一些实施例中，栅极可以包括具有第一长度的第一栅极; 具有第二长度的两个第二栅极，其布置成使得第一栅极设置在第二栅极之间; 以及两个第三栅极，其布置成使得所述第二栅极布置在所述第三栅极之间; 并且第一，第二和第三长度可以全部不同。在一些实施例中，栅极可以包括与第二组栅极交替布置的第一组栅极，间隔物可以布置在第一组的栅极与第二组的栅极之间，并且第一组或第二组中的栅极可以包括具有U形横截面的栅极电介质。

50. 发明申请

WO2017213651A1 QUANTUM DOT DEVICES WITH TOP GATES 审中-公开
标题翻译：量子点设备与顶盖
公开(公告)号：WO2017213651A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036581
申请日：2016-06-09
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , CLARKE, James S. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R.
IPC分类号： H01L29/778 , H01L29/12 , H01L29/66
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of gates disposed on the quantum well stack; and a top gate at least partially disposed on the plurality of gates such that the plurality of gates are at least partially disposed between the top gate and the quantum well stack.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：量子阱堆叠; 设置在量子阱堆叠上的多个栅极; 以及至少部分地设置在所述多个栅极上的顶部栅极，使得所述多个栅极至少部分地设置在顶部栅极和量子阱堆叠之间。

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