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41. 发明申请

US20080227167A1 PROCESS FOR IMMOBILIZED NANO-SIZED METAL PARTICLES 有权
标题翻译：固定的纳米尺寸金属颗粒的方法
公开(公告)号：US20080227167A1
公开(公告)日：2008-09-18
申请号：US12129451
申请日：2008-05-29
申请人： Priyabrata Mukherjee , Absar Ahmad , Deendayal Mandal , Satyajyoti Senapati , Mohammed Islam Khan , Murali Sastry , Rajiv Kumar
发明人： Priyabrata Mukherjee , Absar Ahmad , Deendayal Mandal , Satyajyoti Senapati , Mohammed Islam Khan , Murali Sastry , Rajiv Kumar
IPC分类号： C12P3/00
CPC分类号： C12P1/02 , C12P3/00 , C12R1/645 , Y02E50/17 , Y10S977/703
摘要： The present invention provides a new process using biological method for the preparation of immobilized nano-particles of metals. Fungi are used to efficiently prepare immobilized nano-particles of various metals ions such as Au, Ag, Pd, Pt, Ni, Rh and Ru from their aqueous solutions.
摘要翻译：本发明提供使用生物方法制备金属的固定化纳米颗粒的新方法。真菌用于从其水溶液中有效地制备各种金属离子如Au，Ag，Pd，Pt，Ni，Rh和Ru的固定纳米颗粒。

42. 发明申请

US20070254153A1 Self-Crimping Fully Drawn High Bulky Yarns And Method Of Producing Thereof 有权
标题翻译：自动压接全高拉丝及其生产方法
公开(公告)号：US20070254153A1
公开(公告)日：2007-11-01
申请号：US11632411
申请日：2005-07-14
申请人： Vikas Nadkarni , Santosh Huilgol , Rajiv Kumar
发明人： Vikas Nadkarni , Santosh Huilgol , Rajiv Kumar
IPC分类号： D02G3/02
CPC分类号： D02G3/045 , Y10T428/2924 , Y10T428/2929 , Y10T428/2931 , Y10T442/3146 , Y10T442/3154
摘要： Self-crimping fully drawn high bulk yarns comprising fibre forming bicomponent filaments comprising two polymers having different crystallizability or differential orientation or combination thereof is disclosed herein. Further the present invention discloses a method for producing the self-crimping fully drawn high bulk yarns by single and two-stage process. The invention also discloses the fabric comprising the self-crimping fully drawn high bulk yarns.
摘要翻译：本文公开了包含具有不同结晶性或差异取向的两种聚合物或其组合的包含纤维形成双组分长丝的全自动卷曲全松散高体积纱。此外，本发明公开了通过单阶段和两阶段方法生产自卷曲全拉伸高松散纱线的方法。本发明还公开了包括自卷曲全拉伸高松散纱线的织物。

43. 发明申请

US20060171184A1 Low power content addressable memory system and method 有权
标题翻译：低功耗可寻址存储器系统和方法
公开(公告)号：US20060171184A1
公开(公告)日：2006-08-03
申请号：US11321749
申请日：2005-12-29
申请人： Anoop Khurana , Rajiv Kumar
发明人： Anoop Khurana , Rajiv Kumar
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A low power content addressable memory system comprising an array of content addressable memory cells organized as a plurality of equal sized cam cell groups, each cam cell group having one or more cam cells; a valid entry tag bit associated with each said content addressable memory cell; a match output generator connected to the output of each cam cell and an enabling means having its first input connected to the valid entry tag bit, its second input connected to a match control signal and its output connected to the corresponding match output generator such that said match output generator is enabled only if said valid entry tag bit indicates a valid entry.
摘要翻译：一种低功率内容可寻址存储器系统，包括被组织为多个相等尺寸的凸轮单元组的内容可寻址存储器单元的阵列，每个凸轮单元组具有一个或多个凸轮单元; 与每个所述内容可寻址存储器单元相关联的有效输入标签位; 连接到每个凸轮单元的输出的匹配输出发生器和启用装置，其第一输入连接到有效输入标签位，其第二输入连接到匹配控制信号，其输出连接到相应的匹配输出发生器，使得所述匹配输出生成器只有在所述有效条目标签位指示有效条目时被使能。

44. 发明申请

US20060136287A1 Method and apparatus for creating a list for marketing 审中-公开
标题翻译：用于创建营销列表的方法和设备
公开(公告)号：US20060136287A1
公开(公告)日：2006-06-22
申请号：US11022542
申请日：2004-12-22
申请人： Prashant Gupta , Kulo Rajasekaran , Sutirtha Saha , Rajesh Tibrewala , Niroop Singh , Rajiv Kumar , Harvinder Sawhney
发明人： Prashant Gupta , Kulo Rajasekaran , Sutirtha Saha , Rajesh Tibrewala , Niroop Singh , Rajiv Kumar , Harvinder Sawhney
IPC分类号： G06F17/30
CPC分类号： G06Q30/02 , G06Q30/0201
摘要： The method may entail reviewing a source of entries wherein the source is stored electronically, selecting a subset of entries from the source of entries and storing the subset of entries as a list wherein the list comprises a first order object.
摘要翻译：该方法可能需要检查条目源，其中电子地存储源，从条目源选择条目的子集，并将条目的子集存储为列表，其中列表包括第一顺序对象。

45. 发明授权

US06839884B1 Hierarchical functional verification 失效
标题翻译：分层功能验证
公开(公告)号：US06839884B1
公开(公告)日：2005-01-04
申请号：US09766189
申请日：2001-01-18
申请人： Prakash Narain , Rajeev K. Ranjan , Christopher Morrison , John M. Beardslee , Rajiv Kumar
发明人： Prakash Narain , Rajeev K. Ranjan , Christopher Morrison , John M. Beardslee , Rajiv Kumar
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

46. 发明授权

US06654614B2 Implementation of power control in a wireless overlay network 失效
标题翻译：在无线覆盖网络中实现功率控制
公开(公告)号：US06654614B2
公开(公告)日：2003-11-25
申请号：US09347385
申请日：1999-07-06
申请人： Martin Morris , Rajiv Kumar , Lyn Nguyen , Hiep Pham
发明人： Martin Morris , Rajiv Kumar , Lyn Nguyen , Hiep Pham
IPC分类号： H04B138
CPC分类号： H04W52/38 , H04W88/06 , H04W92/02
摘要： A method and apparatus for internetworked communication between first and second wireless networks containing first and second pluralities of wireless nodes, respectively, is disclosed herein. In a preferred implementation a first dual-power node participates in both a first wireless network and an overlay network. The dual-power node is configured to transmit and receive in both a high-power mode and a low-power mode. The dual-power node operates in an overlay network and facilitates data transmission between low-power nodes and high-power nodes by toggling between these two power modes. In a preferred implementation, a third wireless network containing a third plurality of wireless nodes is utilized. The overlay network can accommodate a plurality of high-power or dual-power nodes.
摘要翻译：本文公开了分别包含第一和第二多个无线节点的第一和第二无线网络之间的互联网络通信的方法和装置。在优选实施例中，第一双功率节点参与第一无线网络和覆盖网络。双功率节点配置为在高功率模式和低功耗模式下进行发送和接收。双功率节点在覆盖网络中运行，并且通过在这两个功率模式之间切换来促进低功率节点和高功率节点之间的数据传输。在优选实现中，利用包含第三多个无线节点的第三无线网络。覆盖网络可容纳多个高功率或双功率节点。

47. 发明授权

US06651228B1 Intent-driven functional verification of digital designs 有权
标题翻译：数字设计的意图驱动功能验证
公开(公告)号：US06651228B1
公开(公告)日：2003-11-18
申请号：US09566684
申请日：2000-05-08
申请人： Prakash Narain , Rajiv Kumar , John M. Beardslee , Rajeev K. Ranjan , Christopher R. Morrison
发明人： Prakash Narain , Rajiv Kumar , John M. Beardslee , Rajeev K. Ranjan , Christopher R. Morrison
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.
摘要翻译：提供了一种便于在设计中的关键点之间分析逻辑信号的预期流程的方法和装置。根据本发明的一个方面，可以使用新颖的意图驱动验证过程来检测硬件设计缺陷。首先，接收硬件设计的表示和关于表示中的变量之间的逻辑信号的预期流程的信息。然后，可以基于关于逻辑信号的预期流程的信息来推断硬件设计中的潜在错误的存在，即（1）将关于逻辑信号的预期流程的信息转换成必须在硬件设计的顺序是根据逻辑信号的预期流程进行操作，以及（2）在由硬件设计表示的电路的操作期间确定是否可以违反任何检查。

48. 发明授权

US06559322B1 Process for preparation of a lactone from a cyclic ketone 有权
标题翻译：从环酮制备内酯的方法
公开(公告)号：US06559322B1
公开(公告)日：2003-05-06
申请号：US10032203
申请日：2001-12-21
申请人： Deendayal Mandal , Absar Ahmad , Mohammed Islam Khan , Rajiv Kumar
发明人： Deendayal Mandal , Absar Ahmad , Mohammed Islam Khan , Rajiv Kumar
IPC分类号： C07D31316
CPC分类号： A61L2/186 , A01N25/02 , A01N39/00 , A01N2300/00
摘要： The present invention provides a new biocatalyst whole cell system for converting cyclic ketones such as cyclopentanone/cyclohexanone to the corresponding lactones such as valerolactone/caprolactone. Another novel aspect of the present invention is that biocatalyst fungus Fusarium oxysporum f.sp. ciceri NCIM 1282 species has been found to be an efficient biocatalyst system for any biotransformation for the first time.
摘要翻译：本发明提供了用于将环酮如环戊酮/环己酮转化成相应的内酯如戊内酯/己内酯的新的生物催化剂全细胞系统。本发明的另一个新颖方面是生物催化真菌尖孢镰刀菌（Fusarium oxysporum f.sp.） ciceri NCIM 1282种已被发现是首次用于任何生物转化的有效生物催化剂体系。

49. 发明授权

US06493852B1 Modeling and verifying the intended flow of logical signals in a hardware design 有权
标题翻译：在硬件设计中建模和验证逻辑信号的预期流程
公开(公告)号：US06493852B1
公开(公告)日：2002-12-10
申请号：US09566683
申请日：2000-05-08
申请人： Prakash Narain , Rajiv Kumar
发明人： Prakash Narain , Rajiv Kumar
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a method is provided for explicitly associating state information with variables of a language description of a hardware design. Information regarding the intended flow of logical signals among the variables, which represent interconnects in the hardware design through with the logical signals pass, is received. Then, the intended flow of logical signals is modeled by associating state information with the variables in accordance with the intended flow of logical signals. Advantageously, in this manner, the integrity of the data flow can be verified by confirming checks that are expressed as a function of the states associated with the variables.
摘要翻译：提供了一种便于在设计中的关键点之间分析逻辑信号的预期流程的方法和装置。根据本发明的一个方面，提供了一种用于将状态信息与硬件设计的语言描述的变量明确地相关联的方法。关于在逻辑信号通过中表示硬件设计中的互连的变量之间的逻辑信号的预期流程的信息被接收。然后，通过根据逻辑信号的预期流程将状态信息与变量相关联来建模逻辑信号的预期流程。有利地，以这种方式，可以通过确认作为与变量相关联的状态的函数表示的检查来验证数据流的完整性。

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