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41. 发明专利

DE10197143T5 未知
公开(公告)号：DE10197143T5
公开(公告)日：2004-04-29
申请号：DE10197143
申请日：2001-12-21
申请人： INTEL CORP
发明人： POISNER DAVID , OOI THIEN ERN
IPC分类号： G06F13/24
摘要： An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt if no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

42. 发明专利

AU2003247595A1 SLEEP PROTECTION 未知
公开(公告)号：AU2003247595A1
公开(公告)日：2004-01-19
申请号：AU2003247595
申请日：2003-06-20
申请人： INTEL CORP
发明人： GRAWCOCK DAVID , POISNER DAVID
IPC分类号： G06F21/24 , G06F1/00 , G06F21/00
摘要： Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security enhanced environment and decrypt the secrets in response to a wake event.

43. 发明专利

AU2003231237A1 SYSTEM AND METHOD FOR PROTECTION AGAINST UNTRUSTED SYSTEM MANAGEMENT CODE BY REDIRECTING A SYSTEM MANAGEMENT INTERRUPT AND CREATING A VIRTUAL MACHINE CONTAINER 未知
公开(公告)号：AU2003231237A1
公开(公告)日：2003-12-22
申请号：AU2003231237
申请日：2003-05-01
申请人： INTEL CORP
发明人： GRAWROCK DAVID , UHLIG RICHARD , POISNER DAVID , GLEW ANDREW , HALL CLIFFORD , SMITH LAWRENCE III , NEIGER GILBERT , KOZUCH MICHAEL , GEORGE ROBERT , BURGESS BRADLEY , SUTTON JAMES II
IPC分类号： G06F1/00 , G06F9/46 , G06F12/14 , G06F21/00 , G06F9/40
摘要： Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system management mode VMM (SVMM), which exists in a separate portion of memory from a main virtual machine monitor (MVMM) used to handle virtualization events other than those related to the sub-operating system mode. In at least one embodiment, a technique for initializing and managing transitions to and from the SVMM is disclosed.

44. 发明专利

AU2003223587A1 PROTECTION AGAINST MEMORY ATTACKS FOLLOWING RESET 未知
公开(公告)号：AU2003223587A1
公开(公告)日：2003-11-03
申请号：AU2003223587
申请日：2003-04-10
申请人： INTEL CORP
发明人： GRAWROCK DAVID , POISNER DAVID , SUTTON JAMES II
IPC分类号： G06F12/14 , G06F21/00 , G06F1/00
摘要： Methods, apparatus and computer readable medium are described that attempt to protect secrets from system reset attacks. In some embodiments, the memory is locked after a system reset and secrets removed from the memory before the memory is unlocked.

46. 发明专利

DE60326081D1 未知
公开(公告)号：DE60326081D1
公开(公告)日：2009-03-19
申请号：DE60326081
申请日：2003-10-23
申请人： INTEL CORP
发明人： POISNER DAVID
IPC分类号： G06F13/00 , G06F13/24
摘要： Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

47. 发明专利

DE602005012434D1 未知
公开(公告)号：DE602005012434D1
公开(公告)日：2009-03-05
申请号：DE602005012434
申请日：2005-11-17
申请人： INTEL CORP
发明人： POISNER DAVID , STEVENS WILLIAM
IPC分类号： G06F11/14
摘要： In some embodiment, an arrangement is provided to prevent a loss of data in a memory due to a power failure for a computing system. When the power failure occurs, any pending memory write operations may be completed and dirty cache lines may be flushed back to the memory. Subsequently, the computing system may be put into a loss-prevention state, under which power may be turned off for all components in the computing system except the memory. The memory is powered by a battery pack which includes batteries and is in a self refresh state. When the power returns, applications and operating systems running in the computing system may resume what is left out when the power supply failure occurs, based at least in part on data retained in the memory. Other embodiments are described and claimed.

48. 发明专利

AT422260T 未知
公开(公告)号：AT422260T
公开(公告)日：2009-02-15
申请号：AT03781375
申请日：2003-10-23
申请人： INTEL CORP
发明人： POISNER DAVID
IPC分类号： G06F13/24
摘要： Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

49. 发明专利

DE10392619B4 未知
公开(公告)号：DE10392619B4
公开(公告)日：2008-10-16
申请号：DE10392619
申请日：2003-04-02
申请人： INTEL CORP
发明人： CUI YING , SAMSON ERIC , BERKOVITS ARIEL , NAVALE ADITYA , WYATT DAVID , CLINE LESLIE , TSANG JOSEPH , BLAKE MARK , POISNER DAVID , STEVENS WILLIAM JR , SAR-DESSAI VIJAY
IPC分类号： G06F1/04 , G06F1/32 , G06T1/00
摘要： In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

50. 发明专利

GB2423847B Hardware coordination of power management activities 未知
公开(公告)号：GB2423847B
公开(公告)日：2007-01-10
申请号：GB0609876
申请日：2004-11-16
申请人： INTEL CORP
发明人： WILCOX JEFFREY R , KAUSHIK SHIVNANDAN , GUNTHER STEPHEN H , BODAS DEVADATTA V , RAMAKRISHNAN SIVA , POISNER DAVID , LINT BERNARD J , HACKING LANCE E
IPC分类号： G06F1/26 , G06F1/32 , G06F12/08
摘要： Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

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