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41. 发明授权

US07824989B2 Method for reducing overlap capacitance in field effect transistors 有权
标题翻译：降低场效应晶体管重叠电容的方法
公开(公告)号：US07824989B2
公开(公告)日：2010-11-02
申请号：US12050596
申请日：2008-03-18
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.
摘要翻译：一种用于形成场效应晶体管（FET）器件的方法包括在半导体衬底上形成栅极导体; 形成源极区域，所述源极区域具有在所述栅极导体下方重叠并延伸的源极延伸部; 以及形成漏极区域，所述漏极区域具有漏极延伸部，所述漏极延伸部沿所述栅极的宽度在选定位置处重叠并延伸到所述栅极导体下方; 并且所述漏极区域还包括对应于所述漏极延伸部不重叠并在所述栅极导体下方延伸的区域的多个凹陷区域，其中所述多个凹陷区域仅形成在所述漏极区域中。

42. 发明授权

US07312134B2 Dual stressed SOI substrates 有权
标题翻译：双重应力SOI衬底
公开(公告)号：US07312134B2
公开(公告)日：2007-12-25
申请号：US11741441
申请日：2007-04-27
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

43. 发明申请

US20080299732A1 METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 失效
标题翻译：减少场效应晶体管重叠电容的方法
公开(公告)号：US20080299732A1
公开(公告)日：2008-12-04
申请号：US12173098
申请日：2008-07-15
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
摘要翻译：场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域仅沿着栅极导体的宽度的选定位置。

44. 发明申请

US20080166848A1 METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS 有权
标题翻译：减少场效应晶体管重叠电容的方法
公开(公告)号：US20080166848A1
公开(公告)日：2008-07-10
申请号：US12050596
申请日：2008-03-18
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain region, the drain region having a drain extension that overlaps and extends under the gate conductor at selected locations along the width of the gate; and the drain region further comprising a plurality of recessed areas corresponding to areas where the drain extension does not overlap and extend under the gate conductor, wherein the plurality of recessed areas is formed only in the drain region.
摘要翻译：一种用于形成场效应晶体管（FET）器件的方法包括在半导体衬底上形成栅极导体; 形成源极区域，所述源极区域具有在所述栅极导体下方重叠并延伸的源极延伸部; 以及形成漏极区域，所述漏极区域具有漏极延伸部，所述漏极延伸部沿所述栅极的宽度在选定位置处重叠并延伸到所述栅极导体下方; 并且所述漏极区域还包括对应于所述漏极延伸部不重叠并在所述栅极导体下方延伸的区域的多个凹陷区域，其中所述多个凹陷区域仅形成在所述漏极区域中。

45. 发明申请

US20080142852A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS 审中-公开
标题翻译：具有不同表面方向的主动区域的半导体器件结构
公开(公告)号：US20080142852A1
公开(公告)日：2008-06-19
申请号：US12032913
申请日：2008-02-18
申请人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

46. 发明授权

US07355245B2 Structure for reducing overlap capacitance in field effect transistors 有权
标题翻译：降低场效应晶体管重叠电容的结构
公开(公告)号：US07355245B2
公开(公告)日：2008-04-08
申请号：US11692453
申请日：2007-03-28
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L29/76
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
摘要翻译：场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域仅沿着栅极导体的宽度的选定位置。

47. 发明授权

US07253482B2 Structure for reducing overlap capacitance in field effect transistors 失效
标题翻译：降低场效应晶体管重叠电容的结构
公开(公告)号：US07253482B2
公开(公告)日：2007-08-07
申请号：US11161447
申请日：2005-08-03
申请人： Huilong Zhu , Oleg Gluschenkov
发明人： Huilong Zhu , Oleg Gluschenkov
IPC分类号： H01L29/76
CPC分类号： H01L29/6656 , H01L21/26506 , H01L21/26586 , H01L21/7624 , H01L29/66659 , H01L29/7835
摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.
摘要翻译：场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域仅沿着栅极导体的宽度的选定位置。

48. 发明授权

US07247547B2 Method of fabricating a field effect transistor having improved junctions 失效
标题翻译：制造具有改善结的场效晶体管的方法
公开(公告)号：US07247547B2
公开(公告)日：2007-07-24
申请号：US10905454
申请日：2005-01-05
申请人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
发明人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/26506 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.
摘要翻译：提供一种形成场效应晶体管的方法，其包括从单晶半导体区域形成具有第一深度的非晶化半导体区域，随后在非晶化半导体区域的沟道部分的上方形成第一栅极导体。然后将包括n型掺杂剂和p型掺杂剂中的至少一种的第一掺杂剂注入第二深度到不被第一栅极导体掩蔽的非晶化半导体区域的部分，以形成与沟道相邻的源极/漏极部分一部分。然后将衬底加热以使非晶化半导体区域的沟道部分和源极/漏极部分重结晶。在加热步骤之后，至少部分重结晶的半导体区域被局部加热以在沟道部分和源极/漏极部分中的至少一个中激活掺杂剂。

49. 发明申请

US20050269561A1 Strained Si on multiple materials for bulk or SOI substrates 有权
标题翻译：应变Si在多种材料上用于体或SOI衬底
公开(公告)号：US20050269561A1
公开(公告)日：2005-12-08
申请号：US10859736
申请日：2004-06-03
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/10 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层。

50. 发明授权

US08227316B2 Method for manufacturing double gate finFET with asymmetric halo 有权
标题翻译：制造具有不对称卤素的双栅极finFET的方法
公开(公告)号：US08227316B2
公开(公告)日：2012-07-24
申请号：US11427409
申请日：2006-06-29
申请人： Huilong Zhu , Oleg Gluschenkov , Jing Wang
发明人： Huilong Zhu , Oleg Gluschenkov , Jing Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/78612 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.
摘要翻译： finFet使用两个栅极结构之一来控制传导通道条件，优选地具有比另一个栅极结构更短的栅极长度，以限制在导电沟道上相对的电容。以与栅极结构相邻的角度执行的用于控制导通通道条件的不对称卤素杂质注入形成了超陡逆行阱，以限制由另一栅极结构控制的导电沟道部分中的短沟道效应。

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