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41. 发明申请

US20110001536A1 STATIC LATCH 审中-公开
标题翻译：静态锁
公开(公告)号：US20110001536A1
公开(公告)日：2011-01-06
申请号：US12496712
申请日：2009-07-02
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A static latch includes a clock-based driver, an actuation circuit, and a weak latched unit. The clock-based driver includes first node, second node, a driving unit, first pass switch, and second pass switch. The driving unit drives the first node corresponding to first voltage in response to first level of an input signal and drives the second node having second voltage in response to second level of the input signal. The first pass switch drives an output node having a latched signal corresponding to the first voltage in response to the clock signal. The second pass switch drives the output node corresponding to the second voltage in response to the inverted clock signal. The actuation circuit drives the output node corresponding to the second voltage in response to the clock signal. The weak latch unit keeps the level of the latched signal when the static latch is disabled.
摘要翻译：静态锁存器包括基于时钟的驱动器，致动电路和弱锁存单元。基于时钟的驱动器包括第一节点，第二节点，驱动单元，第一遍开关和第二遍开关。驱动单元响应于输入信号的第一级驱动对应于第一电压的第一节点，并响应于输入信号的第二电平驱动具有第二电压的第二节点。第一通路开关响应于时钟信号驱动具有对应于第一电压的锁存信号的输出节点。响应于反相时钟信号，第二通路开关驱动对应于第二电压的输出节点。致动电路响应于时钟信号驱动与第二电压对应的输出节点。当禁止静态锁存时，弱锁存单元保持锁存信号的电平。

42. 发明授权

US07863934B2 Adjusting method and circuit using the same 有权
标题翻译：调整方法和电路使用相同
公开(公告)号：US07863934B2
公开(公告)日：2011-01-04
申请号：US12144723
申请日：2008-06-24
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： H03K19/094
CPC分类号： H03K19/01
摘要： A method adjusts driving ability of an output buffer. The output buffer has multiple driving ability classes. The method includes the following steps. First, the driving ability of the output buffer is initialized as an initial class among the driving ability classes. Next, a voltage at an output terminal of the output buffer is initialized to an initial voltage. Then, an input voltage is inputted via the input terminal at a first time instant. Next, an output voltage outputted from the output terminal is sampled to obtain a voltage value at a second time instant. Then, whether the voltage value satisfies a predetermined condition is judged. Next, if the voltage value satisfies the predetermined condition, the driving ability class of the output buffer is recorded and set.
摘要翻译：一种调整输出缓冲器的驱动能力的方法。输出缓冲区具有多个驱动能力等级。该方法包括以下步骤。首先，将驱动能力等级初始化为输出缓冲器的驱动能力。接下来，将输出缓冲器的输出端子处的电压初始化为初始电压。然后，在第一时刻通过输入端子输入输入电压。接下来，从输出端子输出的输出电压被采样以在第二时刻获得电压值。然后，判断电压值是否满足预定条件。接下来，如果电压值满足预定条件，则记录和设置输出缓冲器的驱动能力等级。

43. 发明申请

US20100301918A1 Level Shifter and Level Shifting Method Thereof 有权
标题翻译：水平移位器及其移位方法
公开(公告)号：US20100301918A1
公开(公告)日：2010-12-02
申请号：US12854616
申请日：2010-08-11
申请人： Yung-Feng Lin , Chun-Hsiung Hung
发明人： Yung-Feng Lin , Chun-Hsiung Hung
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356182
摘要： A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.
摘要翻译：电平移位器包括第一电平转换装置和第二电平转换装置。第一电平切换装置包括第一开关装置，第二开关装置，第一控制开关和第三开关装置。第一开关装置用于接收输入电压并输出第一电压。第二开关装置耦合到第一开关装置，用于根据第一电压输出第一工作电压作为输出电压。第一控制开关耦合到第一开关装置以接收第一电压。第三开关装置耦合在第一控制开关和第一工作电压之间并由输出电压控制。第二电平切换装置耦合到第一电平切换装置，用于接收输入电压，并因此输出第二工作电压作为输出电压。

44. 发明授权

US07787298B2 Method for preventing memory from generating leakage current and memory thereof 有权
标题翻译：防止存储器产生泄漏电流的方法及其存储器
公开(公告)号：US07787298B2
公开(公告)日：2010-08-31
申请号：US12289576
申请日：2008-10-30
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0408
摘要： A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.
摘要翻译：公开了一种防止存储器产生泄漏电流的方法。存储器包括边界存储器单元和相邻存储器单元。相邻存储单元与边界存储单元相邻。该方法包括以下步骤。相邻存储单元的第一端子通过金属线连接到第二端子。

45. 发明授权

US07724595B2 Current-mode sense amplifier and sense amplifying method 有权
标题翻译：电流模式读出放大器和感测放大法
公开(公告)号：US07724595B2
公开(公告)日：2010-05-25
申请号：US11970545
申请日：2008-01-08
申请人： Yung-Feng Lin , Chun-Yi Lee
发明人： Yung-Feng Lin , Chun-Yi Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/067 , G11C7/08 , G11C16/28 , G11C2207/063
摘要： A current-mode sense amplifier comprises a first current mirror, a second current mirror and an amplifying circuit. The first current mirror outputs a cell current to a memory cell and duplicates the cell current to generate a mirrored cell current. The second current mirror outputs a reference current to the reference cell and duplicates the reference current to generate a mirrored reference current. The amplifying circuit comprises a first switch, second switch, third switch and fourth switch. The first switch has first and second terminals for respectively receiving the mirrored cell and reference currents. The second and third switches have first terminals respectively coupled to the first and second terminals of the first switch, and control terminals respectively coupled to the second and first terminals of the first switch. The fourth switch is connected to second terminals of the second and third switches.
摘要翻译：电流模式读出放大器包括第一电流镜，第二电流镜和放大电路。第一电流镜将单元电流输出到存储单元并复制单元电流以产生镜像单元电流。第二电流镜将参考电流输出到参考单元并复制参考电流以产生镜像参考电流。放大电路包括第一开关，第二开关，第三开关和第四开关。第一开关具有用于分别接收镜像单元和参考电流的第一和第二端子。第二和第三开关具有分别耦合到第一开关的第一和第二端子的第一端子和分别耦合到第一开关的第二端子和第一端子的控制端子。第四开关连接到第二和第三开关的第二端子。

46. 发明授权

US07697349B2 Word line boost circuit and method 有权
标题翻译：字线升压电路及方法
公开(公告)号：US07697349B2
公开(公告)日：2010-04-13
申请号：US11896177
申请日：2007-08-30
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G11C5/01
CPC分类号： G11C8/08 , G11C5/143 , G11C5/145 , H02M3/073
摘要： A word line boost circuit includes a first pump circuit, a first transistor, a voltage detection circuit and a second pump circuit. The first pump circuit provides a gate boosted signal according to an address transfer detection (ATD) signal. The first transistor has a control terminal for receiving the gate boosted signal and a second terminal coupled to a target word line. The voltage detection circuit is for detecting a voltage level of the gate boosted signal and accordingly outputting a detection signal. The second pump circuit is for outputting a boost signal to a first terminal of the first transistor according to a voltage level of the detection signal. The boost signal boosts the target word line via the turned-on first transistor.
摘要翻译：字线升压电路包括第一泵电路，第一晶体管，电压检测电路和第二泵电路。第一泵电路根据地址转移检测（ATD）信号提供门升压信号。第一晶体管具有用于接收栅极升压信号的控制端子和耦合到目标字线的第二端子。电压检测电路用于检测栅极升压信号的电压电平，从而输出检测信号。第二泵电路用于根据检测信号的电压电平将升压信号输出到第一晶体管的第一端。升压信号经由导通的第一晶体管升高目标字线。

47. 发明授权

US06618848B2 Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect 有权
标题翻译：设计非相邻金属位线的电路布局以减少耦合效应的方法
公开(公告)号：US06618848B2
公开(公告)日：2003-09-09
申请号：US09814409
申请日：2001-03-22
申请人： Han-Sung Chen , Kuo-Yu Liao , Yung-Feng Lin , Chun-Hsiung Hung , Ho-Chun Liou
发明人： Han-Sung Chen , Kuo-Yu Liao , Yung-Feng Lin , Chun-Hsiung Hung , Ho-Chun Liou
IPC分类号： G06F1750
CPC分类号： G11C7/18 , G11C17/12
摘要： A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired in the sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. In this way, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.
摘要翻译：公开了一种用于设计不相邻金属位线的电路布局以减少感测操作中的耦合效应的方法。该方法包括提供具有顺序布置的多个位线的存储器阵列，其中每两个相邻位线在存储器阵列中的存储器单元的感测操作中配对。通过分配互相排列的第一对位线来创建第一实施例以产生非相邻位线布局。通过将第二对位线中的一个插入到第一对位线中以在布局设计中分离第一对位线来呈现第二实施例。该方法还包括收缩两个相邻非配对位线之间的布局空间。以这种方式，通过将金属位线的电路布局修改为存储器阵列中的非相邻位线布置，该方法有助于减少金属位线耦合效应，而不会降低集成电路密度。

48. 发明授权

US08693260B2 Memory array with two-phase bit line precharge 有权
标题翻译：具有两相位线预充电的存储器阵列
公开(公告)号：US08693260B2
公开(公告)日：2014-04-08
申请号：US13089835
申请日：2011-04-19
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G11C11/4063
CPC分类号： G11C7/12 , G11C16/24 , G11C16/28
摘要： An integrated circuit includes an array of memory cells with a plurality of columns and rows. A plurality of data lines is coupled to the columns in the array and a plurality of word lines is coupled to the rows in the array. Clamp transistors are coupled to respective data lines in the plurality of data lines, and adapted to prevent voltage on the respective bit lines from overshooting a target level during a precharge interval. A bias circuit is coupled to the clamp transistors on the plurality of bit lines, and arranged to apply the bias voltage in at least two phases within a precharge interval, and to prevent overshoot of the target level on the bit line.
摘要翻译：集成电路包括具有多个列和行的存储器单元的阵列。多个数据线耦合到阵列中的列，并且多个字线耦合到阵列中的行。钳位晶体管耦合到多条数据线中的相应数据线，并且适于防止相应位线上的电压在预充电间隔期间过冲目标电平。偏置电路耦合到多个位线上的钳位晶体管，并且被布置为在预充电间隔内以至少两个相位施加偏置电压，并且防止位线上的目标电平的过冲。

49. 发明申请

US20110133814A1 TX OUTPUT COMBINING METHOD BETWEEN DIFFERENT BANDS 有权
标题翻译： TX输出组合方法在不同的BANDS之间
公开(公告)号：US20110133814A1
公开(公告)日：2011-06-09
申请号：US12789579
申请日：2010-05-28
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： H03K17/687
CPC分类号： H03K17/10 , H03K19/018528
摘要： An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage.
摘要翻译：输出缓冲器包括第一输出晶体管，第一开关，第二开关和第三开关。第一输出晶体管连接到用于输出第一工作电压的第一工作电压作为数据信号。第一开关连接到第一输出晶体管的大部分，用于接收使能信号。第二开关连接到第一开关和用于接收使能信号的第二工作电压，其中第二工作电压低于第一工作电压。第三开关包括连接到第一输出晶体管的主体的第一端子，连接到第一开关的控制端子和连接到第一工作电压的第二端子。

50. 发明申请

US20110051525A1 POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY 有权
标题翻译：节电方法及其半导体存储器的电路
公开(公告)号：US20110051525A1
公开(公告)日：2011-03-03
申请号：US12942222
申请日：2010-11-09
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G11C5/14 , G11C16/30 , G11C11/34
CPC分类号： G11C8/08 , G11C8/06
摘要： A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.
摘要翻译：提供了一种半导体存储器的省电方法。一种用于半导体存储器的省电方法，包括以下步骤：接收多个地址码，每个地址码具有第一部分码和第二部分码; 以及当当前接收到的地址码的第一部分码与最后接收到的地址码的第一部分码不同时激活第一升级处理，否则启动第二加强处理。

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