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    • 44. 发明授权
    • Liquid crystal display and thin film transistor array panel therefor
    • 液晶显示器和薄膜晶体管阵列面板
    • US08228452B2
    • 2012-07-24
    • US12630249
    • 2009-12-03
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • G02F1/1343
    • G02F1/1368G02F1/13624G02F2001/134345H01L27/1255
    • A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
    • 提供薄膜晶体管阵列面板,其包括:绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层,形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在所述数据线和所述第一和第二漏电极上的钝化层; 以及分别电连接到第一和第二电极的第一和第二像素电极,其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。
    • 49. 发明申请
    • THIN FILM TRANSISTOR SUBSTRATE
    • 薄膜晶体管基板
    • US20090141207A1
    • 2009-06-04
    • US12255908
    • 2008-10-22
    • Yoon-Sung UMHoon KimHye-Ran YouJae-Jin LyuSeung-Beom Park
    • Yoon-Sung UMHoon KimHye-Ran YouJae-Jin LyuSeung-Beom Park
    • G02F1/136H01L29/04H01L21/00
    • H01L29/6675G02F1/13624G02F2001/134345H01L27/1288
    • In a thin film transistor, first and second thin film transistors are connected to an Nth gate line and an Mth data line, and first and second sub pixel electrodes are connected to the first and second thin film transistors, respectively. A third thin film transistor includes a gate electrode connected to an (N+1)th gate line, a semiconductor layer overlapping with the gate electrode, a source electrode connected to the second sub pixel electrode and partially overlapping with the gate electrode, and a drain electrode facing the source electrode. A first auxiliary electrode is connected to the drain electrode and arranged on the same layer as the first and second sub pixel electrodes. An opposite electrode is arranged on the same layer as the gate line and at least partially overlaps with the first auxiliary electrode with at least one insulating layer disposed therebetween.
    • 在薄膜晶体管中,第一和第二薄膜晶体管连接到第N栅极线和第M数据线,第一和第二子像素电极分别连接到第一和第二薄膜晶体管。 第三薄膜晶体管包括连接到第(N + 1)栅极线的栅电极,与栅电极重叠的半导体层,连接到第二子像素电极并与栅电极部分重叠的源极, 漏电极面对源电极。 第一辅助电极连接到漏电极并且设置在与第一和第二子像素电极相同的层上。 相对电极布置在与栅极线相同的层上,并且与第一辅助电极至少部分重叠,并且其间设置有至少一个绝缘层。