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41. 发明专利

JP2002182948A TRACE ACQUISITION METHOD AND DEVICE 失效
公开(公告)号：JP2002182948A
公开(公告)日：2002-06-28
申请号：JP2000379769
申请日：2000-12-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YASUDA YOSHIKO , HIGUCHI TATSUO , HAMANAKA NAOKI , SHUDO TAKASHI , TSUJII HIDEAKI
IPC分类号： G06F11/28
摘要： PROBLEM TO BE SOLVED: To provide a trace device and a trace acquisition method for efficiently utilizing a memory and reducing the labor of debugging and tuning a user program. SOLUTION: The trace device is provided with a trace management table holding one or more trace write end addresses and a means for generating a trace write address. At the time of starting trace acquisition, the trace write address generation means reads the write end address held in the trace management table and generates a new trace write address. A means for registering the trace write address to the trace management table when the trace acquisition is ended is provided.

42. 发明专利

JPH11345220A INTER-NODE DATA TRANSFER METHOD AND INTER-COMPUTER DATA TRANSFER METHOD 失效
公开(公告)号：JPH11345220A
公开(公告)日：1999-12-14
申请号：JP16928398
申请日：1998-06-02
申请人： HITACHI LTD
发明人： NAONO TAKESHI , YAMAMOTO YUSAKU , IHARA SHIGEO , ITO SATOSHI , YASUDA YOSHIKO
IPC分类号： G06F15/173 , G06F13/38 , G06F15/163
摘要： PROBLEM TO BE SOLVED: To execute data transfer which makes the whole data to be transferred exist on the whole memories in the shortest time. SOLUTION: This data transfer method performs one side transfer and mutual transfer with other computers and is performed by a parallel computer that consists of plural computers provided with a memory and performs the fastest data transfer by performing mutual transfer two times after performing one side transfer two times at the time of transferring data so as to be stored in the whole computers, for instance, when data D(1) is stored is M(12) among computers 1 to 16 (memories M(1) to M(16)), D(2) in M(10), D(3) in M(11) and D(4) in M(12). Generally, when there are M computers (however, M is the power of 2) and D pieces (however, 1

43. 发明专利

JPH10214259A PARALLEL COMPUTER 失效
公开(公告)号：JPH10214259A
公开(公告)日：1998-08-11
申请号：JP2972297
申请日：1997-01-29
申请人： HITACHI LTD
发明人： FUJII KEIMEI , YASUDA YOSHIKO
IPC分类号： G06F9/46 , G06F15/16 , G06F15/163 , G06F15/17
摘要： PROBLEM TO BE SOLVED: To realize the sharing mechanism of a main storage content at low costs, and to attain the efficient improvement of a coordinated processing between element processors in a parallel computer in a distributed memory system. SOLUTION: A mirror group sharing a main storage content between element processors is defined, and a mirror page corresponding to the group (id) is prepared on a main storage 118 of each element processor. Also, a storage controller 102 is provided with a mirror table 105 which registers the leading address of the mirror page and the group (id), and a main storage writing request in the mirror page is detected by an address analyzing part 104 by referring to the table 105, and the writing request is transmitted to the main storage 118, and also transmitted through an interconnection network 202 to the whole element processors in the mirror group. Thus, a page having the same main storage content is allowed to exist in each element processor in the mirror group, and the pseudo-sharing of the main storage content can be attained.

44. 发明专利

JPH09198358A PROBLEM AREA DIVISION/ALLOCATION SYSTEM AND COMPUTER LIBRARY USING THE SAME 失效
公开(公告)号：JPH09198358A
公开(公告)日：1997-07-31
申请号：JP895796
申请日：1996-01-23
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , TANAKA TERUO
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
摘要： PROBLEM TO BE SOLVED: To provide communication performance equal to that at the time of allocating an area with being conscious of dimensional constitution even if the problem area is divided and the divided area is allocated to a processor without being conscious of the dimensional constitution of a parallel computer by means of a user. SOLUTION: In the parallel computer which has a network containing grid torus connection in which the number N of the processors can be displayed by the n-th power of a prime (x) (>=2), a means 1-1 for deciding the number (m) of dimensions on the problem area in a range which does not exceed (n), a means 1-3 for deciding an area division method among area division methods satisfying the power of logx N>=logx (n1 ×n2 ×n3 ×...×n), n1 , n2 , n3 ,..., and n=x(>=2) when the number of the respective dimensional grids of a physical space is set to be n1 , n2 , n3 ,..., and a means 1-4 for allocating the devided area to the processor having the same physical number as a divided area number which is one-dimensionally displayed are provided.

45. 发明专利

JPH08185380A PARALLEL COMPUTER 失效
公开(公告)号：JPH08185380A
公开(公告)日：1996-07-16
申请号：JP32676894
申请日：1994-12-28
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , TANAKA TERUO
IPC分类号： G06F15/173 , G06F15/80 , G06F15/163
摘要： PURPOSE: To provide a parallel computer capable of approximately uniforming the load of a transfer route in a network and easing interference between different kinds of messages and having a network with simple structure. CONSTITUTION: Each processor (PE) determines attribute information while referring to an attribute setting table 305 in accordance with the sort of a message to be transmitted and integrates the determined information in the message. For instance, a route bit RB is set up to '0' or '1' as attribute information in accordance with judgement whether the message is a message autonomously transmitted from a transmitting source PE or a message for informing the reception of another message. Each exchange(EX) refers to a route indication table 601 based upon an RB in a received message and determines a message transfer destination depending upon a receiving PE number specified by the message. Each EX is provided with plural virtual channel circuits 401 to 405, each virtual channel circuit has plural buffers previously allocated correspondingly to different RB values in the message and the received message is stored in the buffer corresponding to the RB value in the message, so that interference between different messages can be reduced.

46. 发明专利

JPH07210528A SWITCH CIRCUIT 失效
公开(公告)号：JPH07210528A
公开(公告)日：1995-08-11
申请号：JP191394
申请日：1994-01-13
申请人： HITACHI LTD
发明人： TANAKA TERUO , YASUDA YOSHIKO
IPC分类号： G06F15/173 , G06F13/362 , G06F13/38
摘要： PURPOSE:To improve the working rate of a switch by reducing the number of idle output ports by storing a message which is forcedly waited by contention arbitration in a FIFO buffer for temporarily storing it. CONSTITUTION:The message selected by switching selectors 14W-14Z is stored in output buffers 15W-15Z by a message contention arbitrating part 11 and transferred through lines L23W-L23Z to the input port of a processor or a switch at a following step. Lines L24W-L24Z are provided for a message transfer suppressing signal from the following step and while this signal is outputted, the message transfer to the following step is suppressed. In this case, a FIFO buffer 13 is provided and the message which is forcedly temporarily waited by the contention caused by transfer requests from the plural input ports to the same output port, can be fetched through a selector 12. Thus, the input port provided with the message waited by the contention is opened, and the next message can be transferred.

47. 发明专利

JPH06282511A FAULT PROCESSING DEVICE OF COMPUTER SYSTEM HAVING NETWORK 失效
公开(公告)号：JPH06282511A
公开(公告)日：1994-10-07
申请号：JP33053193
申请日：1993-12-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI SHIGEO , INAGAMI YASUHIRO , NAKAKOSHI JUNJI , SHUDO SHINICHI , HIGUCHI TATSUO , FUJII KEIMEI , YASUDA YOSHIKO , OBARA KIYOHIRO , TOBA TATSU , YAMADA MASAHIRO
IPC分类号： G06F11/00 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a network which does not affect on other message transfer even if any fault occurs in the process of a message transfer. CONSTITUTION:The fault detected by a fault detector 102 is held in a fault holding register A 110 or a fault holding register B 111, and the detected word number is held in a fault word number holding register 112. When a message generation circuit 120 judges that they are inputted and the fault is detected by a transfer destination processor number, the circuit 120 outputs a message to the processor shown by the transfer destination processor number at the time of the occurrence of the fault to be delivered from a selector 109. Because the message is made to be transferred to a proper processor in place of the transfer destination processor when a fault occurs in the transfer destination processor number of the message, the message does not stop in the network and does not affect on other message transfer.

48. 发明专利

JP2001184321A MAIN MEMORY SHARED PARALLEL COMPUTERS AND NODE CONTROLLER TO BE USED THEREFOR 失效
公开(公告)号：JP2001184321A
公开(公告)日：2001-07-06
申请号：JP36623599
申请日：1999-12-24
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , HAMANAKA NAOKI , SHONAI TORU , AKASHI HIDEYA , TSUSHIMA YUJI , UEHARA KEITARO
IPC分类号： G06F12/08 , G06F15/173 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To improve efficiency in the use of parallel computers by reducing the load of an inter-node interconnection network. SOLUTION: Each of nodes decodes the control information and address information of an access request issued by a processor or I/O device, generates a cache coincidence control flag showing whether cache coincidence control is required or not, a node number to become the object of transfer and a unit number and adds them to the access request. An intra-node interconnection circuit holds the cache coincidence control flag, node number and unit number added to the access request and when the cache coincidence control flag shows the cache coincidence control is not required, and the node number shows the present node, the access request is not transferred to an inter-node interconnection circuit but directly transferred to a unit instructed by the unit number. The inter-node interconnection circuit holds the cache coincidence control flag, the node number and the unit number and when the cache coincidence control flag shows the cache coincidence control is not required, the access request is directly transferred to the node shown by the node number.

49. 发明专利

JPH11126196A DATA TRANSFER METHOD AND COMPUTER SYSTEM SUITABLE FOR THE SAME 失效
公开(公告)号：JPH11126196A
公开(公告)日：1999-05-11
申请号：JP29059797
申请日：1997-10-23
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , FUJII KEIMEI
IPC分类号： G06F15/16 , G06F9/46 , G06F13/00 , G06F15/163 , G06F15/17 , G06F15/173 , G06F15/177 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To accelerate the inter-memory direct transfer through a standard MPI library. SOLUTION: A transmission side PUT/GET library generates a transfer control information 200 in response to a data transmission request command issued from a user process to the MPI library. While using a transmission data address and a transmission flag address in that information, a transmission side network interface circuit reads additional information 714 respectively corresponding to user data 713 and user data to be used by the MPI library out of a local memory and sends it to a network 105 as one message 705, and a transmission end flag 715 is written while using the transmission flag address. A reception side network interface circuit respectively writes the user data and the additional information in local memory areas 721 and 722 designated by a reception data address and a reception flag address in a message and writes a reception completion flag 723 in an area 723.

50. 发明专利

JPH10207848A PARALLEL COMPUTER 失效
公开(公告)号：JPH10207848A
公开(公告)日：1998-08-07
申请号：JP611497
申请日：1997-01-17
申请人： HITACHI LTD
发明人： YASUDA YOSHIKO , FUJII KEIMEI
IPC分类号： G06F15/173 , G06F15/16 , G06F15/80
摘要： PROBLEM TO BE SOLVED: To improve the parallel processing efficiency of a parallel computer. SOLUTION: Each processor has a memory 108 for transfer control which stores data transfer control information showing the storage location, transfer data size, etc., of transmit data in addition to its main storage 104; and memories 108 are operated independently to reduce the overhead of a data transfer process and further to read the transfer control information and read and write data to and from main storages 104 in parallel.

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