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41. 发明授权

US06563155B2 Cross point type DRAM cell composed of a pillar having an active region 有权
标题翻译：由具有活性区域的柱构成的交叉点型DRAM单元
公开(公告)号：US06563155B2
公开(公告)日：2003-05-13
申请号：US09392133
申请日：1999-09-08
申请人： Yoichi Miyai , Hiroyuki Yoshida
发明人： Yoichi Miyai , Hiroyuki Yoshida
IPC分类号： H01L29108
CPC分类号： H01L27/10855 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L29/945
摘要： A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing. A method for manufacturing such a device is also disclosed, and requires only four masks.
摘要翻译：动态随机存取存储器（DRAM）器件包括衬底，多个基本平行的字线和多个基本上平行的位线。在字线和位线的交点处形成多个存储单元。每个存储单元包括从衬底向外延伸的半导体材料的柱。存储节点插头从存储节点经由柱延伸到存储节点接触件和MOS晶体管的漏极和源极之一。位线插头从位线向内延伸到柱的外表面以形成位线接触，并且MOS晶体管的漏极和源极中的另一个。字线插头从字线延伸通过柱，并且字线插头的一部分形成MOS晶体管的栅极。存储节点插头，位线插头和字线插头可以不对称地形成为具有期望的厚度的基本上固体的单一结构，以便于制造。还公开了一种用于制造这种装置的方法，并且仅需要四个掩模。

42. 发明授权

US06519544B1 Method and apparatus for IEEE 1394 bus analysis 有权
标题翻译： IEEE 1394总线分析方法和装置
公开(公告)号：US06519544B1
公开(公告)日：2003-02-11
申请号：US09662141
申请日：2000-09-14
申请人： Tomohiro Deguchi , Hiroyuki Miyazaki , Hiroyuki Yoshida , Minoru Wano
发明人： Tomohiro Deguchi , Hiroyuki Miyazaki , Hiroyuki Yoshida , Minoru Wano
IPC分类号： G06F1900
CPC分类号： G06F11/221
摘要： IEEE 1394 bus interface circuit 15X comprises a physical layer LSI 37 connected to an IEEE 1394 bus 14, a data capture circuit 22X connected to the physical layer LSI 37 through signal lines to capture data on the signal lines for data analysis, and a coupler (a plug or a socket) 38 to be coupled to a coupler (a socket or a plug) 39 to which a physical layer LSI of an IEEE 1394 bus interface 10 is attached in actual use. With engaging the couplers 39 and 38 to each other, data transmitted between nodes 10 and 13 are captured by the data capture circuit 22X and analyzed in an IEEE 1394 bus analysis apparatus 16. In another IEEE 1394 bus interface circuit, a link power status signal provided to the physical layer circuit from the link layer circuit is fixedly set low, whereby the physical layer circuit is made to function as a repeater, and data received by the physical layer circuit are captured by the link layer circuit and analyzed in the IEEE 1394 bus analysis apparatus.
摘要翻译： IEEE 1394总线接口电路15X包括连接到IEEE 1394总线14的物理层LSI 37，通过信号线连接到物理层LSI37的数据捕获电路22X，以捕获用于数据分析的信号线上的数据，以及耦合器耦合到实际使用的IEEE 1394总线接口10的物理层LSI的耦合器（插座或插头）39连接到插座或插座38。通过使耦合器39和38彼此接合，在节点10和13之间传输的数据被数据捕获电路22X捕获并在IEEE 1394总线分析装置16中进行分析。在另一个IEEE 1394总线接口电路中，链路电源状态信号从链路层电路提供给物理层电路固定设置为低，从而使物理层电路作为中继器，由物理层电路接收的数据由链路层电路捕获并在IEEE 1394中进行分析总线分析装置。

43. 发明授权

US06455099B1 Method and device for applying sealant to IC having bumps 失效
标题翻译：用于向具有凸块的IC施加密封剂的方法和装置
公开(公告)号：US06455099B1
公开(公告)日：2002-09-24
申请号：US09763162
申请日：2001-02-16
申请人： Kouhei Enchi , Hiroyuki Yoshida , Yoshifumi Kitayama
发明人： Kouhei Enchi , Hiroyuki Yoshida , Yoshifumi Kitayama
IPC分类号： B05D512
CPC分类号： H01L24/11 , H01L21/56 , H01L21/67126 , H01L21/6715 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/14
摘要： A method and a device for applying a sealant to an IC having bumps, which can solve a cobwebbing problem when a dispense nozzle is raised after the sealant has been applied and implement a productivity improvement; specifically, a method and a device for applying a sealant to an IC having bumps, wherein a dispense nozzle (12) is raised in a first stage (E) at a low speed simultaneously with the stop of dispensing until the first stage (E) covers a specified height and then it is raised in a second stage (F) at a high seed. The above design, in which the dispense nozzle (12) is raised in the first stage (E) at a low speed after the application of the sealant (2) and the nozzle (12) is then raised at a high speed and in a short time in the second stage (F), can positively break off the sealant (2) without inducing cobwebbing and enhance productivity.
摘要翻译：一种用于向具有凸点的IC施加密封剂的方法和装置，其可以解决在施加密封剂之后分配喷嘴升高时的蛛丝网问题，并实现生产率提高; 具体地说，涉及一种向具有凸起的IC施加密封剂的方法和装置，其中分配喷嘴（12）在第一阶段（E）中以低速同时停止分配直到第一阶段（E）升高，覆盖指定的高度，然后在高种子的第二阶段（F）中升高。然后，在施加密封剂（2）和喷嘴（12）之后，其中分配喷嘴（12）在第一阶段（E）中以低速升高的设计然后以高速和在第二阶段（F）的短时间内，可以有效地破坏密封胶（2），而不会产生丝网印刷并提高生产率。

44. 发明授权

US06347269B1 Vehicle mass calculation device 有权
标题翻译：车辆质量计算装置
公开(公告)号：US06347269B1
公开(公告)日：2002-02-12
申请号：US09625985
申请日：2000-07-26
申请人： Kisaburo Hayakawa , Masataka Osawa , Hiroyuki Yoshida , Masuji Oshima
发明人： Kisaburo Hayakawa , Masataka Osawa , Hiroyuki Yoshida , Masuji Oshima
IPC分类号： G01M1500
CPC分类号： G01M17/007 , B60T2250/02 , G01G19/086
摘要： To calculate a vehicle mass based on a driving force caused by an engine, running resistance, and vehicle acceleration, influence of gradient resistance is removed. A gross driving force calculating section calculates a gross driving force F of a vehicle by deducting running resistance from a driving force of a vehicle caused by an engine. An acceleration sensor calculates a longitudinal acceleration &agr; of the vehicle. Relationship among a gross driving force F, a longitudinal acceleration &agr;, a vehicle mass M, and road gradient &THgr; can be expressed as (&agr;=F/M−g sin &THgr;). Because the change of gradient contains only a low frequency component, by processing a gross driving force F and an acceleration &agr;, using a high-pass filter with a predetermined cut-off frequency, the influence of the gradient &THgr; can be removed. Based on the resultant processed gross driving force F and the processed acceleration &agr;, a vehicle mass can be obtained from the above expression without being affected by the influence of the gradient
摘要翻译：为了基于由发动机，行驶阻力和车辆加速度引起的驱动力来计算车辆质量，消除了梯度阻力的影响。总驱动力计算部通过从发动机引起的车辆的驱动力减去行驶阻力来计算车辆的总动力F. 加速度传感器计算车辆的纵向加速度α。总驱动力F，纵向加速度α，车辆质量M和道路坡度＆THgr之间的关系; 可以表示为（α= F / M-g sin＆THgr;）。由于梯度的变化仅包含低频分量，通过使用具有预定截止频率的高通滤波器处理总驱动力F和加速度α，梯度＆THgr; 可以删除基于得到的经处理的总驱动力F和处理的加速度α，可以从上述表达式获得车辆质量，而不受梯度的影响

45. 发明授权

US6055724A Method and device for sealing IC chip 失效
标题翻译：密封IC芯片的方法和装置
公开(公告)号：US6055724A
公开(公告)日：2000-05-02
申请号：US155720
申请日：1998-10-02
申请人： Kenichi Nishino , Shinji Kanayama , Hiroyuki Otani , Kohei Enchi , Hiroyuki Yoshida
发明人： Kenichi Nishino , Shinji Kanayama , Hiroyuki Otani , Kohei Enchi , Hiroyuki Yoshida
IPC分类号： H01L21/60 , H01L21/00 , H01L21/56 , H01L23/28 , H01R43/00 , B23P19/00
CPC分类号： H01L24/27 , H01L21/56 , H01L21/563 , H01L21/67126 , H01L24/28 , H01L2224/73203 , H01L2224/83102 , H01L2224/92125 , H01L2224/92225 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/14 , Y10T29/4913 , Y10T29/49171 , Y10T29/53178
摘要： A method and device for sealing an IC chip are provided, by which a sealing material is surely discharged onto the upper surface of a circuit board, and the occurrence of imperfect sealing can be eliminated. A first gap (h1) is provided between an application nozzle (15) and a circuit board (13) on which an IC chip (12) is mounted before discharging the sealing material (17), after which a second gap (h2) which is greater than the first gap (h1) is provided between the application nozzle (15) and the circuit board (13) while discharging the sealing material (17), thereby accomplishing the sealing of the IC chip (12), and ensuring that the sealing operation is performed after the sealing material (17) has completely come to contact with the upper surface of the circuit board (13).
摘要翻译： PCT No.PCT / JP98 / 00447 Sec。 371日期：1998年10月2日 102（e）1998年10月2日日期PCT提交1998年2月2日PCT公布。第WO98 / 34276号公报日本1998年8月6日提供了一种用于密封IC芯片的方法和装置，通过该方法和装置可靠地将密封材料排出到电路板的上表面上，并且可以消除不完全密封的发生。在排出密封材料（17）之前，在施加喷嘴（15）和安装有IC芯片（12）的电路板（13）之间设置有第一间隙（h1），之后，将第二间隙（h2）大于在排出密封材料（17）时在施加喷嘴（15）和电路板（13）之间提供第一间隙（h1），从而实现IC芯片（12）的密封，并且确保在密封材料（17）完全与电路板（13）的上表面接触之后进行密封操作。

46. 发明授权

US6034920A Semiconductor memory device having a back gate voltage controlled delay circuit 有权
标题翻译：具有背栅电压控制延迟电路的半导体存储器件
公开(公告)号：US6034920A
公开(公告)日：2000-03-07
申请号：US198816
申请日：1998-11-24
申请人： Shunichi Sukegawa , Shinji Bessho , Tadashi Tachibana , Hiroyuki Yoshida
发明人： Shunichi Sukegawa , Shinji Bessho , Tadashi Tachibana , Hiroyuki Yoshida
IPC分类号： G11C7/06 , G11C8/18 , G11C8/00
CPC分类号： G11C8/18 , G11C7/06
摘要： A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.
摘要翻译：半导体存储器件具有地址缓冲器（200,230）。预解码器电路（202,232）接收地址缓冲器（200,230）的输出，存储器阵列（212）接收预解码器电路的输出。主放大器（216,248）又接收存储器阵列（212,244）的输出。地址转换检测器（ATD）脉冲发生器电路（204,234）还接收地址缓冲器（200,230）的输出，并且脉冲延迟电路（208,240）接收地址转换检测器脉冲发生器电路的输出（204,234）。脉冲延迟电路（208,240）还向主放大器（216,248）提供主放大器信号。存储装置还包括产生背栅电压的电压发生器（206,236），该栅极电压作为用于地址转换检测器（ATD）脉冲发生器电路（204,234）的低电压电源（VBB）和脉冲延迟电路（208,240）。地址转换检测器（ATD）脉冲发生器（204,234）和脉冲延迟电路（208,240）具有由背栅极电压（VBB）控制的延迟，并且对高电压源（VDD）的依赖性降低）的存储器件。

47. 发明授权

US6012980A Coordinates detecting device, method for same and game device 失效
标题翻译：坐标检测装置，方法及游戏装置
公开(公告)号：US6012980A
公开(公告)日：2000-01-11
申请号：US875623
申请日：1997-12-11
申请人： Hiroyuki Yoshida , Takeshi Nagashima
发明人： Hiroyuki Yoshida , Takeshi Nagashima
IPC分类号： G01B11/00 , G06F3/037 , F41G3/26
CPC分类号： A63F13/219 , A63F13/04 , A63F13/213 , A63F13/837 , A63F2300/8076
摘要： The coordinates detecting device comprises a plurality of sensors (LS1, LS2: photosensors, or the like,) located in prescribed positions in a coordinates detecting region for detecting coordinates set on an image display surface (4) which displays images by means of scanning lines; a counter which counts the number of clock inputs with respect to the horizontal direction of the image display surface and the number of scans in the vertical direction, on the basis of the scan timing of the scanning lines as detected by the sensors; and a coordinates identifying circuit which, when a desired trigger signal (LP3) is input from an external source, outputs the count values of the counters at the time that this trigger signal is input as relative coordinates on the image display surface. The coordinates of any position can be determined accurately even when the display uses a special television format, such as HDTV, or the like, and regardless of differences in the scanning system.
摘要翻译： PCT No.PCT / JP96 / 03001 Sec。 371 1997年12月11日第 102（e）日期1997年12月11日PCT提交1996年10月16日PCT公布。出版物WO97 / 21071 日期1997年6月12日坐标检测装置包括位于坐标检测区域中的规定位置的多个传感器（LS1，LS2：光电传感器等），用于检测设置在显示图像的图像显示面（4）上的坐标通过扫描线; 基于由传感器检测的扫描线的扫描定时，计数相对于图像显示面的水平方向的时钟输入的数量和垂直方向的扫描次数的计数器; 以及坐标识别电路，当从外部源输入期望的触发信号（LP3）时，输出该触发信号输入时的计数器的计数值作为图像显示面上的相对坐标。即使显示器使用诸如HDTV等的特殊电视格式，也可以准确地确定任何位置的坐标，并且不管扫描系统的差异如何。

48. 发明授权

US5740268A Computer-aided method for image feature analysis and diagnosis in mammography 失效
标题翻译：计算机辅助方法用于乳腺摄影术中的图像特征分析和诊断
公开(公告)号：US5740268A
公开(公告)日：1998-04-14
申请号：US536253
申请日：1995-09-29
申请人： Robert M. Nishikawa , Takehiro Ema , Hiroyuki Yoshida , Kunio Doi
发明人： Robert M. Nishikawa , Takehiro Ema , Hiroyuki Yoshida , Kunio Doi
IPC分类号： A61B6/00 , G06F19/00 , G06K9/52 , G06T7/00 , G06K9/00
CPC分类号： G06T7/0012 , A61B6/5258 , G06K9/527 , G06T2207/10116 , G06T2207/20064 , G06T2207/30068 , Y10S128/925
摘要： A method for automated detection of abnormal anatomic regions, wherein a mammogram is digitized to produce a digital image and the digital image is processed using local edge gradient analysis and linear pattern analysis in addition to feature extraction routines to identify abnormal anatomic regions. Noise reduction filtering and pit-filling/spike-removal filtering techniques are also provided. Multiple difference imaging techniques are also used in which difference images employing different filter characteristics are obtained and processing results logically OR'ed to identify abnormal anatomic regions. In another embodiment the processing results with and without noise reduction filtering are logically AND'ed to improve detection sensitivity. Also, in another embodiment the wavelet transform is utilized in the identification and detection of abnormal regions. The wavelet transform is preferably used in conjunction with the difference imaging technique with the results of the two techniques being logically OR'ed.
摘要翻译：一种用于自动检测异常解剖区域的方法，其中乳房X线照片被数字化以产生数字图像，并且除了特征提取例程以识别异常解剖区域之外，还使用局部边缘梯度分析和线性模式分析处理数字图像。还提供降噪滤波和凹坑填充/尖峰去除滤波技术。还使用多重差分成像技术，其中获得采用不同滤光器特征的差异图像，并且逻辑上OR'的处理结果用于识别异常解剖区域。在另一个实施例中，具有和不具有噪声降低滤波的处理结果被逻辑地“和”以提高检测灵敏度。此外，在另一实施例中，小波变换用于异常区域的识别和检测。小波变换优选与差分成像技术结合使用，两种技术的结果在逻辑上是有逻辑关系的。

49. 发明授权

US5687688A Vertical engine 失效
标题翻译：垂直发动机
公开(公告)号：US5687688A
公开(公告)日：1997-11-18
申请号：US534969
申请日：1995-09-28
申请人： Masaki Tsunoda , Tetsu Wada , Yoshimi Watanabe , Hiroyuki Yoshida
发明人： Masaki Tsunoda , Tetsu Wada , Yoshimi Watanabe , Hiroyuki Yoshida
IPC分类号： F02B61/04 , F02B75/00 , F02B75/02 , F02B75/18 , F02B75/20 , F02F7/00 , F01M11/02
CPC分类号： F02B75/007 , F02B61/045 , F02B75/20 , F02B2075/027 , F02B2075/1816 , F02F7/006
摘要： In a vertical engine having a crankshaft directed in a vertical direction and a flywheel provided on a lower end of the crankshaft projected through a bottom wall of a crank chamber, the crank chamber is formed by a skirt section integral with a cylinder block and a split crankcase attached to the skirt section putting respective contacting faces together and an oil dropping hole is formed in a bearing wall section provided on the cylinder block side and forming a lowest crank bearing section within the crank chamber. The oil dropping hole communicates with an lower side of the bearing wall section and an upper side of the bearing wall section positioned within a lowest cylinder and is inclined downward from the cylinder side to the contacting face of the skirt section facing to the split crankcase. A flywheel space is formed under the bottom wall of the crank chamber and an oil pan is provided under the flywheel space. An oil return passage extending from the crank chamber to the oil pan detours around the flywheel space.
摘要翻译：在具有沿垂直方向引导的曲轴的垂直发动机和设置在曲轴的下端上的飞轮通过曲轴室的底壁突出，曲轴室由与气缸体一体的裙部形成，连接到裙部的曲轴箱将各接触面放置在一起，并且在设置在气缸体侧的轴承壁部分中形成油滴孔，并在曲柄室内形成最低曲柄轴承部分。漏油孔与支承壁部的下侧连通，并且支承壁部的上侧位于最下部的气缸内，并且从气缸侧朝向与分体曲轴箱相对的裙部的接触面向下倾斜。在曲轴室的底壁下方形成飞轮空间，在飞轮空间下方设置油盘。从曲柄室延伸到油盘的回油通道围绕飞轮空间绕行。

50. 发明授权

US5673332A Computer-aided method for image feature analysis and diagnosis in mammography 失效
标题翻译：计算机辅助方法用于乳腺摄影术中的图像特征分析和诊断
公开(公告)号：US5673332A
公开(公告)日：1997-09-30
申请号：US693502
申请日：1996-08-08
申请人： Robert M. Nishikawa , Takehiro Ema , Hiroyuki Yoshida , Kunio Doi
发明人： Robert M. Nishikawa , Takehiro Ema , Hiroyuki Yoshida , Kunio Doi
IPC分类号： A61B6/00 , G06F19/00 , G06K9/52 , G06T7/00 , G06K9/00
CPC分类号： G06T7/0012 , A61B6/5258 , G06K9/527 , G06T2207/10116 , G06T2207/20064 , G06T2207/30068 , Y10S128/925
摘要： A method for automated detection of abnormal anatomic regions, wherein a mammogram is digitized to produce a digital image and the digital image is processed using local edge gradient analysis and linear pattern analysis in addition to feature extraction routines to identify abnormal anatomic regions. Noise reduction filtering and pit-filling/spike-removal filtering techniques are also provided. Multiple difference imaging techniques are also used in which difference images employing different filter characteristics are obtained and processing results logically OR'ed to identify abnormal anatomic regions. In another embodiment the processing results with and without noise reduction filtering are logically AND'ed to improve detection sensitivity. Also, in another embodiment the wavelet transform is utilized in the identification and detection of abnormal regions. The wavelet transform is preferably used in conjunction with the difference imaging technique with the results of the two techniques being logically OR'ed.
摘要翻译：用于自动检测异常解剖区域的方法，其中乳房X线照片被数字化以产生数字图像，并且除了特征提取例程以识别异常解剖区域之外，还使用局部边缘梯度分析和线性模式分析处理数字图像。还提供降噪滤波和凹坑填充/尖峰去除滤波技术。还使用多重差分成像技术，其中获得采用不同滤光器特征的差异图像，并且逻辑上OR'的处理结果用于识别异常解剖区域。在另一个实施例中，具有和不具有噪声降低滤波的处理结果被逻辑地“和”以提高检测灵敏度。此外，在另一实施例中，小波变换用于异常区域的识别和检测。小波变换优选与差分成像技术结合使用，两种技术的结果在逻辑上是有逻辑关系的。

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