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41. 发明授权

US06334316B1 Desiccant assisted air conditioning system 失效
标题翻译：干燥剂辅助空调系统
公开(公告)号：US06334316B1
公开(公告)日：2002-01-01
申请号：US09581819
申请日：2000-06-19
申请人： Kensaku Maeda , Yoshiro Fukasaku , Hideo Inaba , Toshiaki Oouchi , Rosuke Nishida
发明人： Kensaku Maeda , Yoshiro Fukasaku , Hideo Inaba , Toshiaki Oouchi , Rosuke Nishida
IPC分类号： F25D1706
CPC分类号： F24F3/1423 , B01D53/261 , B01D53/28 , F24F5/001 , F24F2203/1016 , F24F2203/1028 , F24F2203/1036 , F24F2203/104 , F24F2203/1056 , F24F2203/1072 , F24F2203/1076 , F24F2203/1084 , Y02B30/52
摘要： A compact and energy efficient air conditioning system is operated with a desiccant material having a high differential adsorption capacity even at lower regeneration temperatures than those in the conventional system. The desiccant assisted air conditioning system comprises a process air path (A) for flowing process air to adsorb moisture from the process air by a desiccant member, and a regeneration air path (B) for flowing regeneration air heated by a heat source to desorb moisture from the desiccant member (103). The desiccant member is arranged so that the process air or the regeneration air flows alternatingly through the desiccant member. The desiccant member is arranged so that the process air or the regeneration air flows alternatingly through the desiccant member. The desiccant member comprises an organic polymer material, the organic polymer material comprising an amphoteric ion exchange polymer having an anion exchange group, a cation exchange group and bridging ligands, thereby exhibiting a high differential adsorption capacity.
摘要翻译：即使在比常规系统中更低的再生温度下，紧凑且节能的空调系统也使用具有高差分吸附能力的干燥剂材料来操作。干燥剂辅助空调系统包括用于使处理空气流动以通过干燥剂部件吸收来自处理空气的水分的处理空气路径（A）和用于使由热源加热的再生空气流动以再生水分的再生空气路径（B）来自干燥剂构件（103）。干燥剂构件被布置成使得处理空气或再生空气交替地流过干燥剂构件。干燥剂构件被布置成使得处理空气或再生空气交替地流过干燥剂构件。干燥剂构件包括有机聚合物材料，该有机聚合物材料包含具有阴离子交换基团的两性离子交换聚合物，阳离子交换基团和桥连配位体，从而表现出高的差异吸附能力。

42. 发明授权

US6137732A Semiconductor memory device having voltage boosting circuit 有权
标题翻译：具有升压电路的半导体存储器件
公开(公告)号：US6137732A
公开(公告)日：2000-10-24
申请号：US313078
申请日：1999-05-17
申请人： Hideo Inaba
发明人： Hideo Inaba
IPC分类号： G11C11/413 , G11C8/08 , G11C16/06 , G11C16/30 , G11C16/04
CPC分类号： G11C16/30 , G11C8/08
摘要： A semiconductor memory device has a ring oscillator that is configured so that its period in the time before reaching a raised voltage is made short and further so that its period after reaching the raised voltage is made long, and a voltage boosting circuit that raises the voltage on a word line of memory cells, based on a boosted potential that is output from the ring oscillator. The ring oscillator performs a plurality of voltage boosting operations until the boosted potential of the word line of the memory cells reaches the voltage that is required for writing of data thereinto, and makes the period of the ring oscillator output ROC short while performing the plurality of boosting operations, and makes the period of the ring oscillator output ROC long after a prescribed raised voltage level is reached, thereby reducing the amount of AC current that flows in the ring oscillator itself.
摘要翻译：半导体存储器件具有环形振荡器，其被配置为使得其在达到升高的电压之前的时间段被进一步缩短，使得其达到升高的电压之后的周期变长，并且提高电压的升压电路在存储器单元的字线上，基于从环形振荡器输出的升压电位。环形振荡器执行多个升压操作，直到存储单元的字线的升压电位达到其中写入数据所需的电压，并且使得环形振荡器输出ROC的周期在执行多个升压操作，并且在达到规定的升高电压电平之后使环形振荡器输出ROC的周期长，从而减少在环形振荡器本身中流动的AC电流量。

43. 发明授权

US5936911A Static type semiconductor memory device with timer circuit 失效
标题翻译：带定时电路的静态型半导体存储器件
公开(公告)号：US5936911A
公开(公告)日：1999-08-10
申请号：US19404
申请日：1998-02-05
申请人： Hideo Inaba
发明人： Hideo Inaba
IPC分类号： G11C11/413 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/18 , G11C11/418 , G11C13/00
CPC分类号： G11C8/08 , G11C11/18 , G11C11/418 , G11C8/10 , G11C8/18
摘要： In a static type semiconductor memory device, a word decoder is connected to a plurality of word lines to decode an address signal to select one of the plurality of word lines. A resistor load type memory cell is connected to said selected word line. The resistor load type memory cell is composed of two pairs of a load resistor and a MOS transistor and the two pairs are connected to form a flip-flop. A word line voltage boosting circuit is connected to the word decoder to boost a voltage of the selected word line to a voltage higher than a power supply voltage in response to a boost control signal. A timer circuit includes a replica of the load transistor of one of the two pair and replicas of the MOS transistors of the two pair. The timer circuit generates the boost control signal for a predetermined time period in response to a start control signal to activate said word line voltage boosting circuit.
摘要翻译：在静态型半导体存储器件中，字解码器被连接到多个字线以解码地址信号以选择多个字线中的一个。电阻器负载型存储单元连接到所述选择的字线。电阻负载型存储单元由两对负载电阻和MOS晶体管组成，并且两对连接形成触发器。字线电压升压电路连接到字解码器，以响应于升压控制信号将所选字线的电压升高到高于电源电压的电压。定时器电路包括两对的MOS晶体管的两对和复制品之一的负载晶体管的副本。定时器电路响应于启动控制信号而产生预定时间段的升压控制信号以激活所述字线升压电路。

44. 发明授权

US5357461A Output unit incorporated in semiconductor integrated circuit for preventing semiconductor substrate from fluctuating in voltage level 失效
标题翻译：半导体集成电路中的输出单元，用于防止半导体衬底在电压水平上波动
公开(公告)号：US5357461A
公开(公告)日：1994-10-18
申请号：US778653
申请日：1991-10-18
申请人： Hideo Inaba
发明人： Hideo Inaba
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K19/003 , H03K19/0948 , G11C7/00 , G11C7/02
CPC分类号： H03K19/00361 , H03K17/162
摘要： An output circuit is incorporated in an integrated circuit for communicating with an external device, and includes a plurality of output inverting circuits. Each such inverting circuit is implemented by a series combination of a p-channel enhancement type field effect transistor and an n-channel enhancement type field effect transistor. The inverting circuits are coupled between a positive power voltage line and a ground voltage line electrically connected with a semiconductor substrate. The output circuit also includes a plurality of output pins, each coupled between an external load and one of the output inverting circuits, and a resistive element coupled between the ground voltage line and the semiconductor substrate, so that the ground voltage line hardly fluctuates in voltage level upon concurrent switching actions of the output inverting circuits.
摘要翻译：输出电路结合在用于与外部设备通信的集成电路中，并且包括多个输出反相电路。每个这样的反相电路由p沟道增强型场效应晶体管和n沟道增强型场效应晶体管的串联组合来实现。反相电路耦合在正电源电压线和与半导体衬底电连接的接地电压线之间。输出电路还包括多个输出引脚，每个输出引脚分别耦合在一个外部负载和一个输出反相电路之间，以及耦合在接地电压线和半导体基板之间的电阻元件，使得接地电压线几乎不在电压上波动输出反相电路并联切换动作时的电平。

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