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41. 发明授权

US06567313B2 Nonvolatile memory, semiconductor device and method of programming to nonvolatile memory 有权
公开(公告)号：US06567313B2
公开(公告)日：2003-05-20
申请号：US09964394
申请日：2001-09-28
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

42. 发明授权

US06512398B1 Semiconductor integrated circuit device having reference voltage generating section 失效
标题翻译：具有参考电压产生部分的半导体集成电路器件
公开(公告)号：US06512398B1
公开(公告)日：2003-01-28
申请号：US09572443
申请日：2000-05-17
申请人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
发明人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
IPC分类号： G01R1900
CPC分类号： G11C5/143 , G01R19/16552 , G05F3/242 , G11C16/30
摘要： The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.
摘要翻译：通过最小化由于制造过程和/或其他因素导致的电源电压的检测水平的波动，可以显着提高半导体集成电路器件的可靠性。在根据本发明的半导体集成电路器件中，差分放大器电路SA放大表示由参考电压产生部分16产生的参考电压VREF与由电源电压VCC分压所获得的检测电压之间的差异的差分电压，电阻器27和28并将其输出作为检测信号K.参考电压产生部分16从由温度和制造过程影响最小的双极晶体管的基极 - 发射极电压产生参考电压VREF，使得检测的波动电源电压VCC的电平可以最小化。

43. 发明授权

US07924615B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07924615B2
公开(公告)日：2011-04-12
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C11/34
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

44. 发明授权

US07652924B2 Data processing circuit for contactless IC card 有权
标题翻译：非接触式IC卡数据处理电路
公开(公告)号：US07652924B2
公开(公告)日：2010-01-26
申请号：US12171724
申请日：2008-07-11
申请人： Yoshiki Kawajiri , Masaaki Terasawa , Takanori Yamazoe
发明人： Yoshiki Kawajiri , Masaaki Terasawa , Takanori Yamazoe
IPC分类号： G11C16/04
CPC分类号： G11C5/145 , G11C16/12
摘要： The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.
摘要翻译：本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为选择时钟信号到电荷泵以将电压升高到预定的电压电平。以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

45. 发明授权

US07376015B2 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 失效
标题翻译：非易失性存储器，半导体器件和编程到非易失性存储器的方法
公开(公告)号：US07376015B2
公开(公告)日：2008-05-20
申请号：US11197588
申请日：2005-08-05
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
摘要翻译：公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

46. 发明申请

US20080019162A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20080019162A1
公开(公告)日：2008-01-24
申请号：US11758108
申请日：2007-06-05
申请人： Taku OGURA , Masaaki Mihara , Yoshiki Kawajiri
发明人： Taku OGURA , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C14/00 , G11C14/0063
摘要： This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.
摘要翻译：这种非易失性半导体存储器件包括一个触发器，其中每个由串联连接的负载晶体管和存储晶体管组成的两个反相器是交叉连接的; 以及两个栅极晶体管，每个分别在触发器的一侧分别连接到触发器的节点。反相器的存储晶体管由存储晶体管构成，其可以通过将电子注入其栅极附近来控制阈值电压。该非易失性半导体存储装置还包括两个位线，每个位线连接到两个栅极晶体管中的相应一个; 连接到两个栅极晶体管的两个栅电极的字线; 连接到逆变器的存储晶体管的源极的第一电源线; 以及与逆变器的负载晶体管的源极连接的第二电压供给线。

47. 发明申请

US20050265114A1 Nonvolatile memory, semiconductor device, and method of programming to nonvolatile memory 失效
标题翻译：非易失性存储器，半导体器件和编程到非易失性存储器的方法
公开(公告)号：US20050265114A1
公开(公告)日：2005-12-01
申请号：US11197588
申请日：2005-08-05
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Kazufumi Suzukawa , Masamichi Fujito , Takashi Yamaki , Kiichi Makuta , Masashi Wada , Yoshiki Kawajiri
IPC分类号： G11C16/02 , G11C8/02 , G11C16/12
CPC分类号： G11C16/3459 , G11C16/12 , G11C2216/14
摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.
摘要翻译：公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

48. 发明授权

US5274601A Semiconductor integrated circuit having a stand-by current reducing circuit 失效
标题翻译：具有备用电流降低电路的半导体集成电路
公开(公告)号：US5274601A
公开(公告)日：1993-12-28
申请号：US972545
申请日：1992-11-06
申请人： Takayuki Kawahara , Yoshiki Kawajiri , Takesada Akiba , Masashi Horiguchi , Takao Watanabe , Goro Kitsukawa , Yasushi Kawase , Toshikazu Tachibana , Masakazu Aoki
发明人： Takayuki Kawahara , Yoshiki Kawajiri , Takesada Akiba , Masashi Horiguchi , Takao Watanabe , Goro Kitsukawa , Yasushi Kawase , Toshikazu Tachibana , Masakazu Aoki
IPC分类号： G11C11/40 , G11C5/14 , G11C8/08 , H01L27/02 , H01L27/06 , H03K19/00 , G11C8/00
CPC分类号： H03K19/0016 , G11C5/14 , G11C8/08
摘要： A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.
摘要翻译：开关晶体管的器件参数被设置为使得构成在待机状态下被截止的电源开关的开关晶体管的漏电流小于P沟道的亚阈值电流的总和或多个CMOS电路处于断开状态的N沟道MOS晶体管。因此，在待机状态下流过多个CMOS电路的电流不由亚阈值电流确定，而是由开关晶体管的小的漏电流确定。结果，即使当CMOS电路收缩并且亚阈值电流增加时，也可以减少待机状态下的电流消耗。

49. 发明申请

US20100149875A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149875A1
公开(公告)日：2010-06-17
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

50. 发明申请

US20070274129A1 Data processing device 失效
标题翻译：数据处理装置
公开(公告)号：US20070274129A1
公开(公告)日：2007-11-29
申请号：US11819974
申请日：2007-06-29
申请人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
发明人： Masaaki Terasawa , Yoshiki Kawajiri , Takanori Yamazoe
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/32
摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.
摘要翻译：从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息读操作中的字线选择电平，而非易失性存储器具有低功耗模式。在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

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