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41. 发明申请

US20120008399A1 METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES 有权
标题翻译：包括表征记忆细胞信号线的记忆的操作方法
公开(公告)号：US20120008399A1
公开(公告)日：2012-01-12
申请号：US13235995
申请日：2011-09-19
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.
摘要翻译：操作存储器的方法有助于补偿存储器单元信号线传播延迟，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。方法包括通过确定存储单元信号线的RC时间常数来选择存储器的存储单元信号线并表征存储单元信号线。

42. 发明申请

US20110122717A1 REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES 有权
标题翻译：在外部地址响应中更换记忆细胞的有缺陷的位点
公开(公告)号：US20110122717A1
公开(公告)日：2011-05-26
申请号：US13017168
申请日：2011-01-31
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/04
CPC分类号： G11C29/848
摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
摘要翻译：提供控制器和存储器件。在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列存储设备。在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列存储单元列的序列的单元，使得无缺陷列替代缺陷列。无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

43. 发明申请

US20110069547A1 SENSING AGAINST A REFERENCE CELL 有权
标题翻译：感染参考细胞
公开(公告)号：US20110069547A1
公开(公告)日：2011-03-24
申请号：US12955419
申请日：2010-11-29
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/28 , G11C16/04
CPC分类号： G11C11/5642 , G11C16/28
摘要： Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.
摘要翻译：公开了存储器件，大容量存储器件和操作存储器的方法，诸如适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的那些。这种存储器件的编程可以包括在表示期望的位模式的范围内对目标阈值电压进行编程。读取这样的存储器件可以包括产生指示目标存储器单元的阈值电压的模拟数据信号。可以相对于参考单元感测目标存储器单元，包括连接到存储器单元的目标串的存储器单元的虚拟串，并且例如通过使用差分放大器来感测参考单元和目标单元之间的差异。这可能允许更广泛的电压范围用于数据状态。

44. 发明授权

US07907444B2 Memory device reference cell programming method and apparatus 有权
标题翻译：存储器件参考单元编程方法和装置
公开(公告)号：US07907444B2
公开(公告)日：2011-03-15
申请号：US12236892
申请日：2008-09-24
申请人： Vishal Sarin , Frankie F. Roohparvar
发明人： Vishal Sarin , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C7/14 , G11C11/5628 , G11C16/0483 , G11C2211/5634
摘要： Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
摘要翻译：公开了存储器件和方法，例如那些有助于整个存储器单元阵列中的参考单元的分配方案的存储器件和方法。例如，一个这样的分配方案按行交错格式分配参考单元，其中每列包含单个参考单元。还公开了以重复或伪随机模式分配的多个参考小区的附加方案。

45. 发明申请

US20110058413A1 MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：在非易失性存储器件中缓解数据从后向模式和程序干扰的破坏
公开(公告)号：US20110058413A1
公开(公告)日：2011-03-10
申请号：US12912027
申请日：2010-10-26
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C16/10 , G11C16/12 , G11C16/26
CPC分类号： G11C16/3418
摘要： In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
摘要翻译：在所公开的实施例之一中，使用写入算法来消除由于存储器单元中的反向图案效应，单元到单元电容耦合和程序干扰引起的错误。要编程的原始数据在存储器单元的初始编程操作之前被调整。然后在另一个编程操作中将原始数据编程到存储器单元中。在替代实施例中，读取调整权重数据值与存储器单元的每个串联串相关联。权重数据值用于补偿在初始字线读取期间读取的数据。在每次读取和读取调整之后更新权重数据值，使得在随后的读取操作中使用经调整的权重数据值。

46. 发明授权

US07881134B2 Replacing defective columns of memory cells in response to external addresses 有权
标题翻译：根据外部地址更换存储单元的有缺陷的列
公开(公告)号：US07881134B2
公开(公告)日：2011-02-01
申请号：US12272138
申请日：2008-11-17
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.
摘要翻译：提供了操作存储器件的电子系统和方法。在一个这样的实施例中，存储器装置接收外部地址，其代替存储器装置的存储器单元列的序列的不存在列的存储器单元的代替存储器列序列的存储器单元的缺陷列使得无缺陷存储器列替换缺陷存储器列。存储器单元的无缺陷列位于存储器单元列中的有缺陷列之后的存储器单元的缺陷列之后的非缺陷列，该存储器单元的列可用于替换存储单元的有缺陷的列。

47. 发明申请

US20110019478A1 SENSING OF MEMORY CELLS IN NAND FLASH 有权
标题翻译：在闪存中感应存储器
公开(公告)号：US20110019478A1
公开(公告)日：2011-01-27
申请号：US12860338
申请日：2010-08-20
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells utilizing source follower voltage sensing. In a source follower sensing or read operation the programmed threshold voltage of a cell in a NAND string of a NAND architecture Flash memory array is read by applying an elevated voltage to the source line, an elevated pass voltage (Vpass) is placed on the gates of the unselected cells of the string to place them in a pass through mode of operation, and a read gate voltage (Vg) is applied to the gate of the selected cell. The selected memory cell operates as a source follower to set a voltage on the coupled bit line at the read gate voltage minus the threshold voltage of the cell (Vg−Vt), allowing the voltage of the cell to be directly sensed or sampled.
摘要翻译：描述了模拟电压NAND架构非易失性存储器数据读取/验证处理和电路，其利用源极跟随器电压感测来感测非易失性单元中的模拟电压。在源跟随器感测或读取操作中，通过向源极线施加升高的电压来读取NAND架构闪存阵列的NAND串中的单元的编程阈值电压，将升高的通过电压（Vpass）放置在栅极的串的未选择的单元以将它们放置在通过工作模式中，并且将读栅极电压（Vg）施加到所选择的单元的栅极。所选择的存储单元作为源极跟随器工作，以在读取栅极电压减去单元的阈值电压（Vg-Vt）来设置耦合位线上的电压，从而允许单元的电压被直接感测或采样。

48. 发明授权

US07872911B2 Non-volatile multilevel memory cells with data read of reference cells 有权
标题翻译：具有参考单元数据读取的非易失性多电平存储单元
公开(公告)号：US07872911B2
公开(公告)日：2011-01-18
申请号：US12504292
申请日：2009-07-16
申请人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
发明人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.
摘要翻译：本公开的实施例提供用于参考单元的数据读取的用于非易失性多级存储器单元数据检索的方法，设备，模块和系统。一种方法包括将耦合到所选字线的多个数据单元的至少一个数据单元编程为对应于目标状态的目标数据阈值电压（Vt）电平; 将耦合到所选字线的多个参考单元的至少一个参考单元编程为目标参考Vt电平，与数据单元数量交织的参考单元的数量; 基于所述至少一个参考单元的数据读取确定参考状态; 以及基于所述至少一个参考单元的改变来改变从所述至少一个数据单元读取的状态。

49. 发明申请

US20110007566A1 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE 有权
公开(公告)号：US20110007566A1
公开(公告)日：2011-01-13
申请号：US12889461
申请日：2010-09-24
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.

50. 发明授权

US07843725B2 M+L bit read column architecture for M bit memory cells 有权
标题翻译：用于M位存储单元的M + L位读取列结构
公开(公告)号：US07843725B2
公开(公告)日：2010-11-30
申请号：US12137171
申请日：2008-06-11
申请人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/16 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C27/005 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program operation to minimize disturb within the pages of the row, while verifying each memory cell page of the row separately. In one embodiment of the present invention, the memory device utilizes data latches to program M-bits of data into each cell of the row and then repurposes the data latches during the subsequent page verify operations to read M+L bits from each cell of the selected page at a higher threshold voltage resolution than required. In sensing, the increased threshold voltage resolution/granularity allows interpretations of the actual programmed state of the memory cell and enables more effective use of data encoding and decoding techniques such as convolutional codes where additional granularity of information is used to make soft decisions reducing the overall memory error rate.
摘要翻译：描述了存储器件和编程和/或读取过程，其在单个程序操作中编程一行非易失性多级存储器单元（MLC），以最小化行的页面内的干扰，同时验证每个存储单元页面的行分开。在本发明的一个实施例中，存储器件利用数据锁存器将M位数据编程到该行的每个单元中，然后在随后的页验证操作期间对数据锁存器进行再调用，以从该存储器的每个单元读取M + L位选择页面的阈值电压分辨率高于所需要的。在感测中，增加的阈值电压分辨率/粒度允许对存储器单元的实际编程状态的解释，并且能够更有效地使用数据编码和解码技术，例如卷积码，其中使用附加粒度信息来做出软判决，从而减少整体内存错误率。

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