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41. 发明授权

US07856072B2 Semiconductor device, memory device and memory module having digital interface 有权
标题翻译：半导体器件，存储器件和具有数字接口的存储器模块
公开(公告)号：US07856072B2
公开(公告)日：2010-12-21
申请号：US12481798
申请日：2009-06-10
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
IPC分类号： H03K9/00 , H03B1/00 , G05F1/10
CPC分类号： H03K5/082 , H03K5/135
摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
摘要翻译：本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时数据。作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

42. 发明授权

US07852145B2 Semiconductor device having power supply system 有权
标题翻译：具有电源系统的半导体装置
公开(公告)号：US07852145B2
公开(公告)日：2010-12-14
申请号：US12320367
申请日：2009-01-23
申请人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
发明人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
IPC分类号： G05F1/10
CPC分类号： H01L23/50 , G06F1/26 , H01L2224/16225 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.
摘要翻译：提供一种半导体器件，包括：第一半导体集成电路; 接地线和电源线槽，其向第一半导体集成电路供电; 以及连接在地线和电源线之间的可变阻抗分量。

43. 发明申请

US20090195295A1 Semiconductor device having power supply system 有权
标题翻译：具有电源系统的半导体装置
公开(公告)号：US20090195295A1
公开(公告)日：2009-08-06
申请号：US12320367
申请日：2009-01-23
申请人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
发明人： Yutaka Uematsu , Hideki Osaka , Tatusya Saito , Yoji Nishio
IPC分类号： G11C5/14
CPC分类号： H01L23/50 , G06F1/26 , H01L2224/16225 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.
摘要翻译：提供一种半导体器件，包括：第一半导体集成电路; 接地线和电源线槽，其向第一半导体集成电路供电; 以及连接在地线和电源线之间的可变阻抗分量。

44. 发明申请

US20090189293A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090189293A1
公开(公告)日：2009-07-30
申请号：US12318700
申请日：2009-01-06
申请人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
发明人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01055 , H01L2924/15311 , H01L2224/05599
摘要： A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.
摘要翻译：具有片上芯片结构的半导体器件由第一半导体芯片和偶数对的第二半导体芯片组成，所有第二半导体芯片在中介层的表面上层压在一起。第一半导体芯片控制每对第二半导体芯片，以激活一个第二半导体芯片，同时使另一个第二半导体芯片失效。第二半导体芯片以通孔和电极通过凸块彼此相对定位的方式配对在一起。由于提供有驱动电压（VDD）的驱动电压电极和提供参考电位（VSS）的参考电位电极在成对的第二半导体芯片之间相互连接在一起，因此可以增加每个第二半导体芯片的总静电电容以便在不增加半导体器件的整体布局面积的情况下显着降低馈送噪声。

45. 发明授权

US07447038B2 Module 有权
标题翻译：模块
公开(公告)号：US07447038B2
公开(公告)日：2008-11-04
申请号：US11304625
申请日：2005-12-16
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： H05K1/00
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
摘要翻译：在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

46. 发明申请

US20080054379A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080054379A1
公开(公告)日：2008-03-06
申请号：US11675476
申请日：2007-02-15
申请人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
发明人： Yoji Nishio , Yutaka Uematsu , Hideki Osaka , Tsutomu Hara , Seiji Funaba
IPC分类号： H01L29/94
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109
摘要： Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.
摘要翻译：输入电路确保参考电压的噪声容限。半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

47. 发明申请

US20060232949A1 Main board for backplane buses 失效
标题翻译：背板总线主板
公开(公告)号：US20060232949A1
公开(公告)日：2006-10-19
申请号：US11404912
申请日：2006-04-17
申请人： Hideki Osaka
发明人： Hideki Osaka
IPC分类号： H05K7/06
CPC分类号： H05K1/0236 , H05K1/0237 , H05K1/0298 , H05K1/167 , H05K2201/044 , H05K2201/09681 , H05K2201/0969
摘要： A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply. An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer-is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.
摘要翻译：提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案，另一层插入空气中）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

48. 发明申请

US20060133055A1 Module 有权
标题翻译：模块
公开(公告)号：US20060133055A1
公开(公告)日：2006-06-22
申请号：US11304625
申请日：2005-12-16
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： H05K7/08
CPC分类号： H05K1/023 , H01L23/50 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48195 , H01L2224/48472 , H01L2224/49 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H05K1/0227 , H05K1/0231 , H05K1/0233 , H05K1/025 , H05K1/181 , H05K2201/093 , H05K2201/09663 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10522 , H05K2201/10545 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.
摘要翻译：在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

49. 发明授权

US06924651B2 Printed board inspecting apparatus 失效
标题翻译：印刷板检测仪器
公开(公告)号：US06924651B2
公开(公告)日：2005-08-02
申请号：US10212209
申请日：2002-08-06
申请人： Hideki Osaka , Toyohiko Komatsu
发明人： Hideki Osaka , Toyohiko Komatsu
IPC分类号： G01R31/02 , G01R5/00 , G01R31/11 , G01R31/28 , G01R27/28 , G01R31/00
CPC分类号： G01R31/11 , G01R31/2806 , Y10T29/49004 , Y10T29/4913
摘要： A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.
摘要翻译：印刷电路板检查装置包括：输入单元，用于输入来自第一信号线的脉冲; 接收单元，用于响应输入的输入脉冲接收在第二信号线中感应的电压; 以及判断单元，用于判断输入脉冲的电压与第二信号线中感应的电压之间的比率是否在预定范围内。使用TDR方法进行检查，以确定耦合度是否在指定值的范围内，并且进行检查以确定极化RZ信号的每个电压，并且脉冲宽度时间在从而使用定向耦合器检查构成总线的印刷电路板和半导体芯片。

50. 发明授权

US06829749B2 Design support apparatus for circuit including directional coupler, design support tool, method of designing circuit, and circuit board 失效
标题翻译：包括定向耦合器，设计支持工具，电路设计方法和电路板在内的电路设计支持设备
公开(公告)号：US06829749B2
公开(公告)日：2004-12-07
申请号：US10214126
申请日：2002-08-08
申请人： Hideki Osaka , Toyohiko Komatsu
发明人： Hideki Osaka , Toyohiko Komatsu
IPC分类号： G06F1750
CPC分类号： H01P5/185 , G06F17/5036 , G06F17/5068 , H01P5/187 , H05K1/0239 , H05K3/0005
摘要： The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.
摘要翻译：减少了通过将主线和短线布置成彼此平行而形成的包括耦合器的电路布局图的步骤数。当制造电路图时，电路图编辑器1902布置存储在元件符号存储部分1904中的耦合器符号100。布局图编辑器1922的布局部分1935通过使用其中限定了耦合器长度和耦合器间隔的电路图信息和耦合器信息来布置构成耦合器的两个布线。布线检查部1936的物体提取部1937从布局图中提取部件和布线，并将其传递到布线检查器1938.此时，耦合器作为不能分解的一个部件被传递到布线检查器。因此，不检查构成耦合器的两条布线之间的间隔。

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