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    • 44. 发明申请
    • Recording device, recording method, and program
    • 记录装置,记录方法和程序
    • US20060127052A1
    • 2006-06-15
    • US10525635
    • 2004-06-09
    • Takashi FurukawaHideki Ando
    • Takashi FurukawaHideki Ando
    • H04N5/91
    • G11B27/034G11B2220/2562
    • The present invention allows a postrecording process to be executed even if a bit rate of data recorded on or data for recording onto a recording medium is higher than a bit rate for reading out from or recording onto the recording medium. At step S363, a control section causes low-res data, which are a data series of sound and picture having the same contents as an audio file of a designated channel, to be read out from an optical disk. At step S367, the control section causes acquired audio data to be recorded to the audio file of the designated channel on the optical disk 7. The present invention is applicable to a disk apparatus for recording audio data and video data onto the optical disk.
    • 即使记录在记录介质上的数据的比特率或用于记录在记录介质上的数据的比特率高于用于从记录介质读出或记录在记录介质上的比特率,本发明允许执行后记录处理。 在步骤363B中,控制部分从光盘读出作为与指定频道的音频文件具有相同内容的声音和图像的数据序列的低分辨率数据。 在步骤S366中,控制部使获取到的音频数据被记录在光盘7上的指定频道的音频文件中。 本发明可应用于将音频数据和视频数据记录在光盘上的盘装置。
    • 48. 发明授权
    • Parallel processing unit which processes branch instructions without
decreased performance when a branch is taken
    • 并行处理单元处理分支指令而不降低执行分支时的性能
    • US5809294A
    • 1998-09-15
    • US594358
    • 1996-01-30
    • Hideki Ando
    • Hideki Ando
    • G06F9/38
    • G06F9/3804G06F9/30072G06F9/3842G06F9/3859
    • A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in the branch-delay slot are those fetched in a period from fetching of the branch instruction till the execution of the branch instruction. Instructions are prefetched from an instruction memory into a queue memory. The queue memory includes a plurality of blocks of storage units. Instructions in the same block as a branch instruction and subsequent to the branch instruction, and instructions in the block adjacent to the block including the branch instruction provide the branch delay slot for the branch instruction. A parallel processing unit operable in a predicted branch method includes a queue memory including a plurality of entries, each of which includes an instruction and a flag indicating that an associated instruction is executed according to a prediction of a branch. This flag is utilized to control execution and non execution of an associated instruction.
    • 以延迟分支方式工作的并行处理单元具有填充了当通过分支指令进行分支时要执行的指令的分支延迟时隙。 分支延迟时隙中的指令是从分支指令的读取到执行分支指令的时间段中获取的指令。 指令从指令存储器预取到队列存储器中。 队列存储器包括多个存储单元块。 与分支指令相同的块中的指令和分支指令之后的指令,以及与包括转移指令的块相邻的块中的指令为分支指令提供分支延迟时隙。 以预测分支方式可操作的并行处理单元包括:包括多个条目的队列存储器,每个条目包括根据分支的预测指示和指示相关联的指令被执行的标志。 该标志用于控制相关指令的执行和非执行。
    • 49. 发明授权
    • System for speculatively executing instructions using multiple commit
condition code storages with instructions selecting a particular storage
    • 用于使用多个提交条件代码存储器推测性地执行指令的系统,其具有选择特定存储器的指令
    • US5771377A
    • 1998-06-23
    • US548374
    • 1995-11-01
    • Hideki Ando
    • Hideki Ando
    • G06F9/32G06F9/38G06F9/45
    • G06F9/3846G06F8/433G06F8/447G06F9/30072G06F9/3808G06F9/3842
    • A processing device executes an instruction speculatively, and execution result of the instruction becomes valid when all the predictions about true/false of branch condition are correct, and the instruction has a commit condition indicating the number of branch conditions. The processing device includes a commit condition decoder for decoding the commit condition; ALU's; a sequential register file for sequentially holding data obtained from ALU; a shadow register file for speculatively holding data obtained from the ALU; true/false register having determination entries, each of which holds undetermined information if true/false of the corresponding branch condition is not yet determined, holds true information if the corresponding branch condition is true, and holds false information if the corresponding branch condition is false; execution control circuit for comparing true/false of an instruction decode entry provided from the commit condition decoder with true/false of the determination entry and controlling the sequential register file to sequentially hold data if they correspond with each other or otherwise controlling the shadow register file to speculatively hold data; and a commit control circuit for comparing true/false of the instruction decode entry with true/false of the determination entry and transferring the data held in the shadow register file to the sequential register file if each true/false of the instruction decode entry coincides with true/false of the corresponding determination entry.
    • 处理装置推测性地执行指令,并且当关于分支条件的真/假的所有预测都是正确的时,指令的执行结果变为有效,并且该指令具有指示分支条件数量的提交条件。 处理装置包括用于对提交条件进行解码的提交条件解码器; ALU的 用于顺序保存从ALU获得的数据的顺序寄存器文件; 用于推测地保持从ALU获得的数据的影子寄存器文件; 具有确定条目的真/假寄存器,如果相应的分支条件的真/假还未确定,则其中的每一个保存未确定的信息,如果相应的分支条件为真,则保持真实信息,并且如果相应的分支条件为假,则保持虚假信息 ; 执行控制电路,用于将从提交条件解码器提供的指令解码条目的真/假与确定条目的真/假进行比较,并且如果它们彼此对应或者以其他方式控制影子寄存器文件,则控制顺序寄存器文件以顺序保存数据 推测持有数据; 以及提交控制电路,用于将指令解码条目的真/假与确定条目的真/假进行比较,并且将保存在影子寄存器文件中的数据传送到顺序寄存器文件,如果指令解码条目的每个真/假与 相应确定条目的真/假。
    • 50. 发明授权
    • Superscalar processor with direct result bypass between execution units
having comparators in execution units for comparing operand and result
addresses and activating results bypassing
    • 具有直接结果的超标量处理器在执行单元之间具有比较器,用于比较操作数和结果地址的执行单元,并激活绕过的结果
    • US5636353A
    • 1997-06-03
    • US225265
    • 1994-04-07
    • Chikako IkenagaHideki Ando
    • Chikako IkenagaHideki Ando
    • G06F9/38
    • G06F9/3824G06F9/3885
    • The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.
    • 所公开的是改进的超标量处理器,用于减少执行指令所需的时间。 超标量处理器包括指令提取级,指令解码级和各自具有流水线结构的功能单元。 功能单元包括执行阶段,存储器访问阶段和回写阶段。 功能单元通过新提供的旁路线连接。 通过其他功能单元(另一个流水线)中的先前执行获得的数据通过旁路管线被应用于用于执行稍后指令的功能单元(流水线)。 执行的数据在管道之间传输而不通过寄存器文件,使得流水线不需要请求执行的数据等待其他流水线的执行的终止。 结果,减少执行指令所需的时间。