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41. 发明授权

US06504763B1 Nonvolatile semiconductor memory capable of random programming 失效
标题翻译：非易失性半导体存储器，能够进行随机编程
公开(公告)号：US06504763B1
公开(公告)日：2003-01-07
申请号：US09683845
申请日：2002-02-21
申请人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/12 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the first conductivity type isolated by an STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate used to provide a first predetermined voltage for the shallow ion well during a data program mode via a conductive plug which electrically connects to the bit line and extends downward to the shallow ion well. Consequently, during a programming operation, only a selected word line is required to have an appropriate voltage applied to it. Thus, the power needed is reduced and access time is shortened.
摘要翻译：能够进行随机编程的非易失性半导体存储器具有具有存储区域的第一导电类型的半导体衬底，位于存储区域内的半导体衬底中的第二导电类型的深离子阱，第一导电类型的浅离子阱通过深离子阱内的STI层隔离，位于浅离子阱内的半导体衬底上的至少一个NAND单元块，以及位于半导体衬底上方的位线，用于为浅离子阱提供第一预定电压通过电连接到位线并向下延伸到浅离子阱的导电插头的数据程序模式。因此，在编程操作期间，仅需要选择的字线来施加适当的电压。因此，所需的功率减少，并且访问时间缩短。

42. 发明授权

US06490196B1 Method for operating a nonvolatile memory having embedded word lines 失效
标题翻译：用于操作具有嵌入字线的非易失性存储器的方法
公开(公告)号：US06490196B1
公开(公告)日：2002-12-03
申请号：US10064047
申请日：2002-06-04
申请人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
发明人： Ching-Hsiang Hsu , Kung-Hong Lee , Ching-Sung Yang
IPC分类号： G11C1604
CPC分类号： H01L29/42336 , G11C8/14 , G11C11/5671 , G11C16/0475 , G11C16/08 , H01L27/115 , H01L29/7883
摘要： A flash memory cell with an embedded gate structure capable of storing two bits of information and the operation of such a flash memory cell are provided. A first ion-doped region, serving as a source terminal, is formed in a semiconductor substrate. An embedded gate structure and a second ion-doped region are alternately arranged on the first ion-doped region. The embedded gate structure is surrounded by the first oxide layer, the trapping layer, and the second oxide layer. An insulating layer is formed on the embedded gate structure. A diffusion drain is positioned atop the second ion-doped region and a conductive layer connects with the diffusion drains. The embedded gate structure is isolated from the diffusion drain with the insulating layer. Furthermore, the reading, programming, and erasing operation of the memory cell with two bits of information are provided.
摘要翻译：提供具有能够存储两位信息的嵌入式门结构和这种闪存单元的操作的闪存单元。作为源极端子的第一离子掺杂区域形成在半导体衬底中。嵌入栅极结构和第二离子掺杂区域交替地布置在第一离子掺杂区域上。嵌入式栅极结构被第一氧化物层，俘获层和第二氧化物层包围。在嵌入式栅极结构上形成绝缘层。扩散漏极位于第二离子掺杂区域顶部，导电层与扩散漏极连接。嵌入式栅极结构与绝缘层与扩散漏极隔离。此外，提供了具有两位信息的存储单元的读取，编程和擦除操作。

43. 发明授权

US08355282B2 Logic-based multiple time programming memory cell 有权
标题翻译：基于逻辑的多时间编程存储单元
公开(公告)号：US08355282B2
公开(公告)日：2013-01-15
申请号：US12818095
申请日：2010-06-17
申请人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
发明人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C2216/10 , H01L27/11519 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
摘要翻译：非易失性存储器系统包括一个或多个非易失性存储器单元。每个非易失性存储单元提供浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。耦合装置位于第一导电区域中。第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。第二浮栅晶体管位于第三导电区域中。这种非易失性存储单元进一步提供两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

44. 发明申请

US20120276700A1 READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：只读存储器及其制造方法
公开(公告)号：US20120276700A1
公开(公告)日：2012-11-01
申请号：US13549525
申请日：2012-07-16
申请人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
发明人： Ching-Hsiang Hsu , Ching-Sung Yang , Shih-Jye Shen
IPC分类号： H01L21/336
CPC分类号： H01L27/112 , G11C17/12 , H01L27/1126
摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.
摘要翻译：掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。第二ROM位包括第二MOS晶体管。

45. 发明申请

US20120236635A1 Logic-Based Multiple Time Programming Memory Cell 有权
标题翻译：基于逻辑的多时间编程存储单元
公开(公告)号：US20120236635A1
公开(公告)日：2012-09-20
申请号：US13485920
申请日：2012-06-01
申请人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
发明人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C16/04 , H01L29/788 , G11C16/10 , G11C16/26 , G11C16/14
CPC分类号： G11C16/0441 , G11C2216/10 , H01L27/11519 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
摘要翻译：非易失性存储器系统包括一个或多个非易失性存储器单元。每个非易失性存储单元包括浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。耦合装置位于第一导电区域中。第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。第二浮栅晶体管位于第三导电区域中。这种非易失性存储单元还包括两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

46. 发明申请

US20090134452A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20090134452A1
公开(公告)日：2009-05-28
申请号：US12341984
申请日：2008-12-22
申请人： Ching-Sung Yang , Wei-Zhe Wong
发明人： Ching-Sung Yang , Wei-Zhe Wong
IPC分类号： H01L29/792
CPC分类号： H01L29/7887 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row.
摘要翻译：非易失性存储器包括衬底，存储器单元阵列，（N + 1）位线，M字线，M个第一控制栅极线和M个第二控制栅极线。存储单元阵列包括N个存储单元列，每个存储单元列包括M个存储单元。（N + 1）位线设置在基板上，并且在列方向上并列布置，并且（N + 1）位线对应于N个存储单元列。 M字线设置在基板上并且在行方向上平行布置。 M个第一控制栅极线在行方向上平行布置在基板上，并且分别连接到同一行中的第一存储单元。 M个第二控制栅极线在行方向上平行布置在基板上，并分别连接到同一行中的第二存储单元。

47. 发明授权

US07491607B2 Method of fabricating flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US07491607B2
公开(公告)日：2009-02-17
申请号：US11750320
申请日：2007-05-17
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/3468 , H01L21/28273 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.
摘要翻译：提供闪存单元。将深井设置在基板中，并将井设置在深井内。层叠栅极结构设置在基板上。源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。选择栅极设置在堆叠的栅极结构和源极区域之间。第一栅极介电层设置在选择栅极和堆叠栅极结构之间。第二栅极电介质层设置在选择栅极和衬底之间。在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。衬底上的导电插塞延伸穿过漏区和深掺杂区。

48. 发明申请

US20080316791A1 OPERATING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY 有权
标题翻译：一次性编程只读存储器的操作方法
公开(公告)号：US20080316791A1
公开(公告)日：2008-12-25
申请号：US12191844
申请日：2008-08-14
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： H01L27/112 , H01L27/11206
摘要： The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.
摘要翻译：本发明提供一种操作一次性可编程只读存储器（OTPROM）的方法。 OTPROM至少包括设置在基板上的选择晶体管，电极和电介质层，其中电极设置在选择晶体管的源极区域上，电介质层被设置在电极和源极区域之间。操作一次性可编程只读存储器的方法包括执行编程操作以将数字数据值“1”写入存储器，并执行编程操作以将数字数据值“0”写入存储器。

49. 发明授权

US07336539B2 Method of operating flash memory cell 有权
标题翻译：操作闪存单元的方法
公开(公告)号：US07336539B2
公开(公告)日：2008-02-26
申请号：US11750323
申请日：2007-05-17
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： G11C16/02 , G11C16/12 , G11C16/14 , G11C16/26
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/3468 , H01L21/28273 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.
摘要翻译：提供闪存单元。将深井设置在基板中，并将井设置在深井内。层叠栅极结构设置在基板上。源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。选择栅极设置在堆叠的栅极结构和源极区域之间。第一栅极介电层设置在选择栅极和堆叠栅极结构之间。第二栅极电介质层设置在选择栅极和衬底之间。在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。衬底上的导电插塞延伸穿过漏区和深掺杂区。

50. 发明申请

US20070259497A1 FABRICATING METHOD OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US20070259497A1
公开(公告)日：2007-11-08
申请号：US11778655
申请日：2007-07-17
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

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