专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

42. 发明申请

US20100197100A1 Semiconductor Devices and Methods of Manufacturing Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100197100A1
公开(公告)日：2010-08-05
申请号：US12762195
申请日：2010-04-16
申请人： Jin-Ping Han , Henry Utomo , O. Sung Kwon , Oh Jung Kwon , Judson Robert Holt , Thomas N. Adam
发明人： Jin-Ping Han , Henry Utomo , O. Sung Kwon , Oh Jung Kwon , Judson Robert Holt , Thomas N. Adam
IPC分类号： H01L21/20 , H01L21/308 , H01L21/336
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供工件，并在工件中形成凹部。凹部具有第一尺寸的深度。在凹部中形成第一半导体材料以将中心区域中的凹部部分地填充到具有第二尺寸的高度。第二维度约为第一维度的一半或更大。第二半导体材料形成在凹部中的第一半导体材料上，以完全填充凹部，第二半导体材料不同于第一半导体材料。

43. 发明申请

US20100148262A1 Resistors and Methods of Manufacture Thereof 审中-公开
标题翻译：电阻器及其制造方法
公开(公告)号：US20100148262A1
公开(公告)日：2010-06-17
申请号：US12336702
申请日：2008-12-17
申请人： Knut Stahrenberg , Karl-Heinz Bach , Manfred Eller , Roland Hampp , Jin-Ping Han , O Sung Kwon
发明人： Knut Stahrenberg , Karl-Heinz Bach , Manfred Eller , Roland Hampp , Jin-Ping Han , O Sung Kwon
IPC分类号： H01L29/772 , H01L21/02
CPC分类号： H01L28/20 , H01L27/0629
摘要： Resistors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a semiconductive material over a workpiece, and patterning at least the semiconductive material, forming a gate of a transistor in a first region of the workpiece and forming a resistor in a second region of the workpiece. At least one substance is implanted into the semiconductive material of the gate of the transistor or the resistor so that the semiconductive material is different for the gate of the transistor and the resistor.
摘要翻译：公开了电阻器，半导体器件及其制造方法。在一个实施例中，制造电阻器的方法包括在工件上形成半导体材料，并且至少构图半导体材料，在工件的第一区域中形成晶体管的栅极，并在第二区域中形成电阻器工件。将至少一种物质注入到晶体管或电阻器的栅极的半导体材料中，使得半导体材料对于晶体管和电阻器的栅极是不同的。

44. 发明授权

US07737468B2 Semiconductor devices having recesses filled with semiconductor materials 有权
标题翻译：具有填充有半导体材料的凹槽的半导体器件
公开(公告)号：US07737468B2
公开(公告)日：2010-06-15
申请号：US11804773
申请日：2007-05-21
申请人： Jin-Ping Han , Henry Utomo , O Sung Kwon , Oh Jung Kwon , Judson Robert Holt , Thomas N. Adam
发明人： Jin-Ping Han , Henry Utomo , O Sung Kwon , Oh Jung Kwon , Judson Robert Holt , Thomas N. Adam
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供工件，并在工件中形成凹部。凹部具有第一尺寸的深度。在凹部中形成第一半导体材料以将中心区域中的凹部部分地填充到具有第二尺寸的高度。第二维度约为第一维度的一半或更大。第二半导体材料形成在凹部中的第一半导体材料上，以完全填充凹部，第二半导体材料不同于第一半导体材料。

45. 发明申请

US20100065922A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100065922A1
公开(公告)日：2010-03-18
申请号：US12626496
申请日：2009-11-25
申请人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
发明人： Jin-Ping Han , Thomas W. Dyer , Henry Utomo , Rajendran Krishnasamy
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。在衬套上形成填充材料。填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

46. 发明申请

US20080305621A1 CHANNEL STRAIN ENGINEERING IN FIELD-EFFECT-TRANSISTOR 有权
标题翻译：场效应晶体管中的通道应变工程
公开(公告)号：US20080305621A1
公开(公告)日：2008-12-11
申请号：US11760056
申请日：2007-06-08
申请人： Thomas Dyer , Rajendran Krishnasamy , Jin-Ping Han , Ernst Demm
发明人： Thomas Dyer , Rajendran Krishnasamy , Jin-Ping Han , Ernst Demm
IPC分类号： H01L21/3205
CPC分类号： H01L29/7845 , H01L21/28026 , H01L21/28079 , H01L21/823807 , H01L29/165 , H01L29/49 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848
摘要： There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.
摘要翻译：公开了一种对包括栅极，源极区和漏极区的场效应晶体管的栅极下面的沟道区域施加应力的方法。该方法包括以下步骤：将应力源嵌入在FET的源极和漏极区域中; 形成覆盖所述栅极和所述源极和漏极区域的应力衬垫; 去除所述应力衬垫的一部分，所述应力衬垫的所述部分位于所述FET的栅极顶部; 去除第一栅极材料的栅极的至少大部分，从而在其中形成开口; 并用第二栅极材料填充开口。

47. 发明申请

US20070196996A1 Semiconductor devices and methods of manufacturing thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070196996A1
公开(公告)日：2007-08-23
申请号：US11356666
申请日：2006-02-17
申请人： Jin-Ping Han , Yung Chong
发明人： Jin-Ping Han , Yung Chong
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/76232 , H01L21/823878 , H01L29/7846
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.
摘要翻译：公开了半导体器件及其制造方法。形成隔离区域，其包括至少部分地衬在工件内形成的沟槽的应力改变材料。隔离区域包括设置在应力变化材料上方的绝缘材料。

48. 发明授权

US6067244A Ferroelectric dynamic random access memory 有权
标题翻译：铁电动态随机存取存储器
公开(公告)号：US6067244A
公开(公告)日：2000-05-23
申请号：US154056
申请日：1998-09-16
申请人： Tso-Ping Ma , Jin-Ping Han
发明人： Tso-Ping Ma , Jin-Ping Han
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223
摘要： A memory including an array of memory cells, each of which includes a ferroelectric field effect transistor (FET) as its memory element; and sense and refresh circuitry connected to the array of memory cells to read stored data within each cell by sensing source-to-drain conductivity of the ferroelectric transistor and to refresh the stored data.
摘要翻译：一种存储器，包括存储单元阵列，每个存储单元包括作为其存储元件的铁电场效应晶体管（FET）; 以及连接到存储器单元阵列的感测和刷新电路，通过感测铁电晶体管的源极 - 漏极电导率并刷新存储的数据来读取每个单元内的存储数据。

49. 发明申请

US20110237039A1 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
标题翻译：形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法
公开(公告)号：US20110237039A1
公开(公告)日：2011-09-29
申请号：US12729486
申请日：2010-03-23
申请人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅极电极上形成掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

50. 发明授权

US08017472B2 CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof 有权
标题翻译：具有衬垫隔离沟槽的应力变化材料的CMOS器件及其制造方法
公开(公告)号：US08017472B2
公开(公告)日：2011-09-13
申请号：US11356666
申请日：2006-02-17
申请人： Jin-Ping Han , Yung Fu (Alfred) Chong
发明人： Jin-Ping Han , Yung Fu (Alfred) Chong
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/76232 , H01L21/823878 , H01L29/7846
摘要： Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.
摘要翻译：公开了半导体器件及其制造方法。形成隔离区域，其包括至少部分地衬在工件内形成的沟槽的应力改变材料。隔离区域包括设置在应力变化材料上方的绝缘材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式