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41. 发明授权

US08384425B2 Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate 有权
标题翻译：具有埋置在绝缘体上半导体衬底的绝缘膜下方的后控制栅极的晶体管阵列
公开(公告)号：US08384425B2
公开(公告)日：2013-02-26
申请号：US12961293
申请日：2010-12-06
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H03K19/173 , H03K3/01 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11807
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上并且包括一组图案，每个图案由至少一个场效应晶体管形成，每个FET晶体管在薄膜中，源极区域，漏极区域，沟道区域和形成在沟道区域上方的前部控制栅极区域。所提供的器件还包括至少一个FET晶体管，其具有包括形成在沟道区域下方的基底衬底中的反向控制栅极区域的图案，所述背栅极区域能够被偏置以便移位晶体管的阈值电压以模拟晶体管的沟道宽度的修改或迫使晶体管保持关断或者在其前控制栅上施加的任何电压。本发明还提供了操作这种半导体器件结构的方法。

42. 发明授权

US08304833B2 Memory cell with a channel buried beneath a dielectric layer 有权
标题翻译：具有埋在电介质层下方的通道的存储单元
公开(公告)号：US08304833B2
公开(公告)日：2012-11-06
申请号：US12974822
申请日：2010-12-21
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H04L27/12
CPC分类号： H01L29/7841 , H01L21/76264 , H01L21/84 , H01L27/0711 , H01L27/10802 , H01L27/1203 , H01L29/1037 , H01L29/1083 , H01L29/4236 , H01L29/66825 , H01L29/7302 , H01L29/7881
摘要： The invention provides various embodiments of a memory cell formed on a semiconductor-on-insulator (SeOI) substrate and comprising one or more FET transistors. Each FET transistor has a source region and a drain region at least portions of which are arranged in the thin layer of the SeOI substrate, a channel region in which a trench is made, and a gate region formed in the trench. Specifically, the source, drain and channel regions also have portions which are arranged also beneath the insulating layer of the SeOI substrate; the portion of channel region beneath the insulating layer extends between the portions of the source and drain regions also beneath the insulating layer; and the trench in the channel region extends into the depth of the base substrate beyond the insulating layer. Also, methods for fabricating such memory cells and memory arrays including a plurality of such memory cells.
摘要翻译：本发明提供了形成在绝缘体上半导体（SeOI）衬底上并且包括一个或多个FET晶体管的存储单元的各种实施例。每个FET晶体管具有源极区和漏极区，其至少部分布置在SeOI衬底的薄层中，其中形成沟槽的沟道区和形成在沟槽中的栅极区。具体地，源极，漏极和沟道区域还具有也被布置在SeOI衬底的绝缘层下方的部分; 绝缘层下方的沟道区域的部分在绝缘层下方的源极和漏极区的部分之间延伸; 并且沟道区域中的沟槽延伸到基底衬底的深度超过绝缘层。而且，制造这种存储单元的方法和包括多个这样的存储单元的存储器阵列。

43. 发明申请

US20120250444A1 PSEUDO-INVERTER CIRCUIT ON SeOI 有权
标题翻译： PSOUD上的PSEUDO-INVERTER电路
公开(公告)号：US20120250444A1
公开(公告)日：2012-10-04
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F3/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

44. 发明申请

US20120231606A1 MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：用于制造半导体器件的多层结构和工艺
公开(公告)号：US20120231606A1
公开(公告)日：2012-09-13
申请号：US13416813
申请日：2012-03-09
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/32 , H01L21/84 , H01L27/1203
摘要： The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
摘要翻译：本发明涉及一种提供绝缘体上硅（SOI）堆叠的方法，其包括衬底层，衬底层上的第一氧化物层和第一氧化物层（BOX层）上的硅层。该方法包括提供SOI堆叠的至少一个第一区域，其中通过热氧化硅层的一部分并提供SOI堆叠的至少一个第二区域来减薄硅层，其中第一氧化物层（BOX层）被稀释通过退火。

45. 发明申请

US20120214291A1 RELAXATION OF STRAINED LAYERS 有权
标题翻译：应变层的松弛
公开(公告)号：US20120214291A1
公开(公告)日：2012-08-23
申请号：US13458587
申请日：2012-04-27
申请人： Fabrice Letertre , Carlos Mazure , Michael R. Krames , Melvin B. McLaurin , Nathan F. Gardner
发明人： Fabrice Letertre , Carlos Mazure , Michael R. Krames , Melvin B. McLaurin , Nathan F. Gardner
IPC分类号： H01L21/762
CPC分类号： H01L21/2007 , H01L21/02422 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L21/3245 , H01L33/0095
摘要： A method for relaxing a layer of a strained material. The method includes depositing a first low-viscosity layer on a first face of a strained material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained material layer; and applying a mechanical pressure to a second face of the strained material layer wherein the second face is opposite to the first face and with the mechanical pressure applied perpendicularly to the strained material layer during at least part of the heat treatment to relax the strained material.
摘要翻译：一种放松应变材料层的方法。该方法包括在应变材料层的第一面上沉积第一低粘度层; 将第一衬底粘合到第一低粘度层以形成第一复合结构; 对所述复合结构进行热处理以使所述第一低粘度层的回流至少部分地松弛所述应变材料层; 以及向所述应变材料层的第二面施加机械压力，其中所述第二面与所述第一面相对，并且在至少部分热处理期间垂直于所述应变材料层施加机械压力以松弛所述应变材料。

46. 发明申请

US20120181609A1 FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER 有权
标题翻译：完全覆盖的SOI器件与BEDIED DOPED层
公开(公告)号：US20120181609A1
公开(公告)日：2012-07-19
申请号：US13305206
申请日：2011-11-28
申请人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
发明人： Gerhard Enders , Wolfgang Hoenlein , Franz Hofman , Carlos Mazure
IPC分类号： H01L27/088 , H01L29/36 , H01L21/8238
CPC分类号： H01L27/10894 , H01L21/84 , H01L27/10876 , H01L27/1207 , H01L29/4236 , H01L29/66621
摘要： The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
摘要翻译：本发明涉及通过提供第一基板来制造半导体器件的方法; 在所述第一衬底的表面区域中提供掺杂层; 在所述掺杂层上提供掩埋氧化物层; 在掩埋氧化物层上提供半导体层以获得绝缘体上半导体（SeOI）晶片; 从所述SeOI晶片的第一区域去除所述掩埋氧化物层和所述半导体层，同时将所述掩埋氧化物层和所述半导体层保持在所述SeOI晶片的第二区域中; 通过在掺杂层中或由掺杂层形成背栅，在第二区域中提供上晶体管; 以及通过在掺杂层中或由掺杂层形成源极和漏极区域来在第一区域中提供下部晶体管。

47. 发明申请

US20110260233A1 DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR 有权
标题翻译：包含绝缘体上的场效应晶体管的器件
公开(公告)号：US20110260233A1
公开(公告)日：2011-10-27
申请号：US12886421
申请日：2010-09-20
申请人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
发明人： Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
IPC分类号： H01L29/788 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823462 , H01L21/823481 , H01L21/84 , H01L27/0705 , H01L27/1203 , H01L27/1207 , H01L29/7881
摘要： The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.
摘要翻译：本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属或半导体层，以及去除掩模和/或图案层。

48. 发明授权

US08035163B2 Low-cost double-structure substrates and methods for their manufacture 有权
标题翻译：低成本双层结构基材及其制造方法
公开(公告)号：US08035163B2
公开(公告)日：2011-10-11
申请号：US12470253
申请日：2009-05-21
申请人： Bich-Yen Nguyen , Carlos Mazure
发明人： Bich-Yen Nguyen , Carlos Mazure
IPC分类号： H01L29/66 , H01L21/30 , H01L21/46
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.
摘要翻译：在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层，结晶半导体层; 以及设置在第二绝缘层上的顶层。此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。本发明还提供了制造这种基材的方法。

49. 发明申请

US20110233675A1 SRAM-TYPE MEMORY CELL 有权
标题翻译： SRAM型存储单元
公开(公告)号：US20110233675A1
公开(公告)日：2011-09-29
申请号：US13039167
申请日：2011-03-02
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/1203
摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.
摘要翻译：一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。第一和第二电位可以根据电池控制操作的类型进行调制。

50. 发明申请

US20110134698A1 FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER 有权
标题翻译：在绝缘层下面有第二个控制栅的闪存存储器
公开(公告)号：US20110134698A1
公开(公告)日：2011-06-09
申请号：US12946135
申请日：2010-11-15
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C16/04 , H01L29/772 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336
摘要： The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
摘要翻译：本发明涉及一种闪存单元，其具有在绝缘体上绝缘体（SOI）衬底上具有浮置栅极的FET晶体管，该半导体材料由通过绝缘掩埋氧化物（BOX）层从基底衬底分离的半导体材料薄膜构成，晶体管在薄膜中具有通道，具有两个控制栅极，位于浮置栅极上方的前控制栅极，并通过栅极间电介质与栅极间绝缘体分离，以及位于绝缘子下方的基底衬底内的反控制栅极（BOX）层，并且仅通过绝缘（BOX）层与沟道分离。两个控制门被设计成组合使用以执行单元编程操作。本发明还涉及由根据本发明的第一方面的多个存储单元组成的存储器阵列，其可以是行和列的阵列，以及制造这种存储单元和存储器阵列的方法。

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