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41. 发明授权

US07254694B2 Processors interconnect fabric with relay broadcasting and accumulation of partial responses 失效
标题翻译：处理器将结构与中继广播和部分响应的积累互连
公开(公告)号：US07254694B2
公开(公告)日：2007-08-07
申请号：US11055297
申请日：2005-02-10
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F9/546
摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.
摘要翻译：数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个处理单位。互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应响应。

42. 发明授权

US08645640B2 Method and apparatus for supporting memory usage throttling 失效
标题翻译：支持内存使用限制的方法和装置
公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。

43. 发明授权

US08683160B2 Method and apparatus for supporting memory usage accounting 失效
标题翻译：支持内存使用计费的方法和装置
公开(公告)号：US08683160B2
公开(公告)日：2014-03-25
申请号：US13165982
申请日：2011-06-22
申请人： Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10 , G06F12/0897
摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访问的结果跟踪每个用户的系统存储器的使用情况。

44. 发明授权

US08650367B2 Method and apparatus for supporting memory usage throttling 失效
公开(公告)号：US08650367B2
公开(公告)日：2014-02-11
申请号：US13585268
申请日：2012-08-14
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.

45. 发明授权

US08161245B2 Method and apparatus for performing data prefetch in a multiprocessor system 失效
标题翻译：在多处理器系统中执行数据预取的方法和装置
公开(公告)号：US08161245B2
公开(公告)日：2012-04-17
申请号：US11054173
申请日：2005-02-09
申请人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , Jeffrey A. Stuecheli
发明人： James S. Fields, Jr. , Benjiman L. Goodman , Guy L. Guthrie , Jeffrey A. Stuecheli
IPC分类号： G06F13/00 , G06F13/28 , G06F15/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0831 , G06F12/0851
摘要： A method and apparatus for performing data prefetch in a multiprocessor system are disclosed. The multiprocessor system includes multiple processors, each having a cache memory. The cache memory is subdivided into multiple slices. A group of prefetch requests is initially issued by a requesting processor in the multiprocessor system. Each prefetch request is intended for one of the respective slices of the cache memory of the requesting processor. In response to the prefetch requests being missed in the cache memory of the requesting processor, the prefetch requests are merged into one combined prefetch request. The combined prefetch request is then sent to the cache memories of all the non-requesting processors within the multiprocessor system. In response to a combined clean response from the cache memories of all the non-requesting processors, data are then obtained for the combined prefetch request from a system memory.
摘要翻译：公开了一种用于在多处理器系统中执行数据预取的方法和装置。多处理器系统包括多个处理器，每个具有高速缓冲存储器。缓存存储器被细分成多个片段。一组预取请求最初由多处理器系统中的请求处理器发出。每个预取请求用于请求处理器的高速缓冲存储器的相应片段之一。响应于在请求处理器的高速缓冲存储器中错过的预取请求，预取请求被合并成一个组合预取请求。然后将组合的预取请求发送到多处理器系统内的所有不请求处理器的高速缓冲存储器。响应于来自所有非请求处理器的高速缓冲存储器的组合清洁响应，然后从系统存储器获得用于组合预取请求的数据。

46. 发明授权

US07484042B2 Data processing system and method for predictively selecting a scope of a prefetch operation 失效
标题翻译：用于预测性地选择预取操作的范围的数据处理系统和方法
公开(公告)号：US07484042B2
公开(公告)日：2009-01-27
申请号：US11465587
申请日：2006-08-18
申请人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.
摘要翻译：数据处理系统至少包括第一和第二相关域，每个域包含至少一个处理单元，耦合第一和第二相干域的互连结构以及第一相干域内的高速缓冲存储器。高速缓冲存储器包括数据阵列，数据阵列的内容的高速缓存目录以及包括预取预测器的高速缓存控制器。预取预测器基于具有不同的第二目标地址的先前的第二预取操作的范围来确定具有第一目标地址的第一预取操作的互连结构上的广播的预测范围。高速缓存控制器以预测的范围在互连结构上发出第一个预取操作。

47. 发明授权

US08645627B2 Memory bus write prioritization 失效
标题翻译：内存总线写优先级
公开(公告)号：US08645627B2
公开(公告)日：2014-02-04
申请号：US13447462
申请日：2012-04-16
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.
摘要翻译：数据处理系统包括包括最低级高速缓存，耦合到多级高速缓存层级的处理器核心以及耦合到最低级高速缓存和存储器系统存储器的存储器总线的存储器控制器的多级高速缓存层级。存储器控制器包括物理读取队列，其缓冲通过存储器总线从系统存储器读取的数据，以及物理写入队列，其通过存储器总线缓冲要写入系统存储器的数据。存储器控制器基于最低级高速缓冲存储器中的多个脏高速缓存线，对存储器总线上的读操作授予优先级。

48. 发明授权

US08838901B2 Coordinated writeback of dirty cachelines 有权
标题翻译：脏缓存行的协调回写
公开(公告)号：US08838901B2
公开(公告)日：2014-09-16
申请号：US12775510
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

49. 发明授权

US08139592B2 Ticket-based operation tracking 失效
标题翻译：基于门票的操作跟踪
公开(公告)号：US08139592B2
公开(公告)日：2012-03-20
申请号：US12124524
申请日：2008-05-21
申请人： Leo J. Clark , James S. Fields, Jr. , Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Leo J. Clark , James S. Fields, Jr. , Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： H04L12/28 , H04L12/56 , G06F13/00 , G06F13/28 , H04H20/71
CPC分类号： G06F12/0831 , G06F12/0897 , G06F12/1458
摘要： A data processing system includes a plurality of processing units coupled by a plurality of communication links for point-to-point communication such that at least some of the communication between multiple different ones of the processing units is transmitted via intermediate processing units among the plurality of processing units. The communication includes operations having a request and a combined response representing a system response to the request. At least each intermediate processing unit includes one or more masters that initiate first operations, a snooper that receives at least second operations initiated by at least one other of the plurality of processing units, a physical queue that stores master tags of first operations initiated by the one or more masters within that processing unit, and a ticketing mechanism that assigns to second operations observed at the intermediate processing unit a ticket number indicating an order of observation with respect to other second operations observed by the intermediate processing unit. The ticketing mechanism provides the ticket number assigned to an operation to the snooper for processing with a combined response of the operation.
摘要翻译：数据处理系统包括由多个通信链路耦合用于点对点通信的多个处理单元，使得多个处理单元中的多个不同处理单元之间的通信中的至少一些通过多个处理单元之间的中间处理单元发送处理单位。该通信包括具有请求的操作和表示对请求的系统响应的组合响应。至少每个中间处理单元包括启动第一操作的一个或多个主机，至少接收由所述多个处理单元中的至少另一个处理单元发起的至少第二操作的侦听器;存储由所述多个处理单元发起的第一操作的主标签的物理队列在该处理单元内的一个或多个主设备，以及票据机构，其分配在中间处理单元处观察到的第二操作，该票单号指示关于由中间处理单元观察到的其他第二操作的观察次序。票务机制将分配给操作员的操作的票号提供给操作的组合响应进行处理。

50. 发明申请

US20080046658A1 Data Processing System and Method for Predictively Selecting a Scope of a Prefetch Operation 失效
标题翻译：用于预测选择预取操作范围的数据处理系统和方法
公开(公告)号：US20080046658A1
公开(公告)日：2008-02-21
申请号：US11465587
申请日：2006-08-18
申请人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F12/0862
摘要： A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.
摘要翻译：数据处理系统至少包括第一和第二相关域，每个域包含至少一个处理单元，耦合第一和第二相干域的互连结构以及第一相干域内的高速缓冲存储器。高速缓冲存储器包括数据阵列，数据阵列的内容的高速缓存目录以及包括预取预测器的高速缓存控制器。预取预测器基于具有不同的第二目标地址的先前的第二预取操作的范围来确定具有第一目标地址的第一预取操作的互连结构上的广播的预测范围。高速缓存控制器以预测的范围在互连结构上发出第一个预取操作。

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