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41. 发明授权

US06405276B1 Selectively flushing buffered transactions in a bus bridge 有权
标题翻译：选择性地刷新总线桥中的缓冲事务
公开(公告)号：US06405276B1
公开(公告)日：2002-06-11
申请号：US09210135
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus. The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the device driver is designed to issue the load request in response to receiving an interrupt or to check status in the device. The source of the interrupt is preferably the target of the load request.
摘要翻译：具有缓冲器集合的总线桥，包括第一和第二缓冲器组。该桥包括用于将由第一外围设备发出的交易指向第一缓冲器组的转向逻辑，以及由第二外围设备向第二缓冲器组发出的事务。总线桥被配置为响应于将第一外围设备识别为由处理器发出的读取请求的目标，在第一缓冲器集合中的延迟读取完成事务之前拉动已存储的写入事务。在一个实施例中，总线桥还被配置为分别从第一和第二外围设备接收第一和第二设备选择信号。在本实施例中，设备选择信号指示由处理器发出的读取请求的目标。在一个实施例中，桥被配置为使得在第一缓冲器组中拉动已发布的存储器写入事务使得除了响应于读取请求不受影响的第一缓冲器集之外的所有缓冲器集中的事务。本发明进一步设想一种计算机系统，其包括经由主机总线和总线桥连接到系统存储器的处理器，其耦合在主机总线和辅助总线之间。该桥最优选地配置为使得由第一外围设备发出的交易存储在第一缓冲器组中，并且由第二外围设备发出的事务存储在第二缓冲器组中。在一个实施例中，设备驱动器被设计为响应于接收到中断或检查设备中的状态而发出加载请求。中断源最好是加载请求的目标。

42. 发明授权

US06295568B1 Method and system for supporting multiple local buses operating at different frequencies 失效
标题翻译：支持多个本地总线工作在不同频率的方法和系统
公开(公告)号：US06295568B1
公开(公告)日：2001-09-25
申请号：US09055414
申请日：1998-04-06
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4022
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. One or more PCI local buses are connected to the system bus through a single PCI host bridge having bus and frequency control logic and bus clocks. The PCI local buses include sets of in-line electronic switches, dividing each PCI local bus into PCI local bus segments for supporting more PCI peripheral component slots then are called out by the PCI local bus standard. The sets of in-line electronic switches are open and closed in accordance with the bus and frequency control logic within the PCI host bridge thereby allowing the PCI peripheral component slots to operate at different bus frequencies, including bus frequencies higher than 66 MHz by using the bus clocks. The sets of in-line electronic switches further allowing different bus segments on the same PCI logical bus to dynamically be operated at different frequencies.
摘要翻译：公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。一个或多个PCI本地总线通过具有总线和频率控制逻辑和总线时钟的单个PCI主机桥连接到系统总线。 PCI本地总线包括一系列在线电子开关，将每个PCI本地总线划分为PCI本地总线段，以支持更多的PCI外设组件插槽，然后由PCI本地总线标准进行调用。这些串联式电子开关根据PCI主机桥内的总线和频率控制逻辑开启和关闭，从而允许PCI外设组件插槽在不同的总线频率下工作，包括高于66MHz的总线频率，通过使用总线时钟这些在线电子开关进一步允许在同一PCI逻辑总线上的不同总线段动态地以不同的频率工作。

43. 发明授权

US06223299B1 Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables 失效
标题翻译：通过坏的奇偶校验或零字节使I / O加载/存储操作到PCI设备的增强的错误处理能够实现
公开(公告)号：US06223299B1
公开(公告)日：2001-04-24
申请号：US09072418
申请日：1998-05-04
申请人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F1100
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
摘要翻译：设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

44. 发明授权

US5761461A Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system 失效
标题翻译：用于防止在数据处理系统内的多个PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5761461A
公开(公告)日：1998-06-02
申请号：US766735
申请日：1996-12-13
申请人： Danny Marvin Neal , Steven Mark Thurber
发明人： Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4027
摘要： A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.
摘要翻译：描述了用于防止在数据处理系统内的分开的外围组件互连（PCI）主机桥的对等访问的方法。根据本发明的方法和系统，在来自PCI设备的访问请求期间，首先确定访问请求是否用于连接到系统总线的系统存储器。响应于确定访问请求不是连接到系统总线的系统存储器，则另外确定访问请求是否用于与请求的PCI设备相同的PCI主机桥下的PCI设备。响应于确定访问请求不是针对与请求的PCI设备相同的PCI主机桥下的PCI设备，拒绝访问请求，使得跨数据处理中的单独PCI主机桥的PCI对等访问系统被阻止。

45. 发明授权

US5673399A System and method for enhancement of system bus to mezzanine bus transactions 失效
标题翻译：将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
申请人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Danny Marvin Neal , Edward John Silha , Steven Mark Thurber
IPC分类号： G06F13/36 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译：数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地，辅助总线将被视为出站交易的目的地和入站交易的来源。主桥包括出站数据路径，入站数据路径和控制机制。出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器回复数据和地址信息。入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。

46. 发明授权

US07099955B1 End node partitioning using LMC for a system area network 有权
标题翻译：对于系统区域网络，使用LMC的端节点分区
公开(公告)号：US07099955B1
公开(公告)日：2006-08-29
申请号：US09692351
申请日：2000-10-19
申请人： Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/173
CPC分类号： H04L29/12254 , H04L29/12783 , H04L61/2038 , H04L61/35 , H04L67/1097 , Y10S707/99932
摘要： A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assigned to select the particular partition in the end node. The Local ID Mask Control (LMC) field is used to assign multiple LIDs to a single port, using those low order bits to then route the message to the appropriate partition in the end node.
摘要翻译：提供了将系统区域网（SAN）数据包路由到单个端节点内的多个分区的方法。本地标识地址（LID）的范围被分配给SAN中的通道适配器端口。然后分配LID中的低位位以选择端节点中的特定分区。本地ID掩码控制（LMC）字段用于将多个LID分配给单个端口，使用这些低位位置将消息路由到最终节点中的相应分区。

47. 发明授权

US08935333B2 Implementing multicast on a system area network channel adapter 有权
标题翻译：在系统区域网络通道适配器上实现组播
公开(公告)号：US08935333B2
公开(公告)日：2015-01-13
申请号：US09925578
申请日：2001-08-09
申请人： Bruce Leroy Beukema , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16 , G06F15/173 , G06F15/167
CPC分类号： H04L12/18
摘要： An apparatus and method for implementing multicast in system area network channel adapters are provided. With the apparatus and method, a multicast packet is received in a channel adapter of an end node. The channel adapter determines which local queue pairs are party of the multicast group identified by a destination local identifier in the multicast data packet. Based on this determination, the channel adapter replicates the data packet and delivers a copy of the data packet to each local queue pair that is part of the multicast group.
摘要翻译：提供了一种用于在系统区域网络信道适配器中实现多播的装置和方法。利用该装置和方法，在端节点的信道适配器中接收到多播分组。信道适配器确定哪个本地队列对是由多播数据分组中的目的地本地标识符标识的多播组的一方。基于该确定，信道适配器复制数据分组，并将数据分组的副本传递给作为多播组一部分的每个本地队列。

48. 发明授权

US07136907B1 Method and system for informing an operating system in a system area network when a new device is connected 有权
标题翻译：连接新设备时通知系统区域网络中的操作系统的方法和系统
公开(公告)号：US07136907B1
公开(公告)日：2006-11-14
申请号：US09692342
申请日：2000-10-19
申请人： Gregory Michael Nordstrom , Renato John Recio , Gregory Francis Pfister , Orvalle Theodore Kirby , Steven Mark Thurber
发明人： Gregory Michael Nordstrom , Renato John Recio , Gregory Francis Pfister , Orvalle Theodore Kirby , Steven Mark Thurber
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： A method and system are provided for dynamically informing an operating system (OS) of a distributed computer system, when a (new) device is added on the network. An OS registers with the subnet administrator (SA) to be notified when a new component is added to the subnet and placed in a partition to which the OS has access. The subnet manager (SM) initializes and configures the new component that is added and, through the partition manager, associates the component to one or more partitions of the subnet. The SA then notifies the OSs with access to the partition(s) to which the component is associated and that have a right to access the new component that the new component is available to the OS. Following, the OS updates a database of available components to include the new component and establishes communication with the new component.
摘要翻译：当在网络上添加（新）设备时，提供了一种用于动态地通知分布式计算机系统的操作系统（OS）的方法和系统。操作系统向子网管理员（SA）注册，当新组件添加到子网并放置在操作系统可以访问的分区时通知该子网。子网管理器（SM）初始化并配置添加的新组件，并通过分区管理器将组件与子网的一个或多个分区相关联。然后，SA通知操作系统对该组件关联的分区的访问，并且有权访问新组件以使新组件可用于OS。以下，OS更新可用组件的数据库以包括新组件并建立与新组件的通信。

49. 发明授权

US07636772B1 Method and apparatus for dynamic retention of system area network management information in non-volatile store 有权
标题翻译：在非易失性存储中动态保留系统区域网络管理信息的方法和装置
公开(公告)号：US07636772B1
公开(公告)日：2009-12-22
申请号：US09692365
申请日：2000-10-19
申请人： Orvalle Theodore Kirby , Gregory Michael Nordstrom , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Orvalle Theodore Kirby , Gregory Michael Nordstrom , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16 , G06F9/00 , G06F13/00
CPC分类号： G06F13/4022
摘要： A method in a network computing system for managing configuration information for a set of components in a network computing system. The configuration information is stored for the set of components in the network computing system to form stored configuration information. In the depicted examples, the components may be nodes or devices within nodes. Current configuration is obtained in response to a power cycle. The current configuration information is compared with the stored configuration information to form a comparison. The stored configuration information is updated if a difference is present in the comparison. The stored configuration information is used to configure the components when a power cycle occurs.
摘要翻译：一种用于管理网络计算系统中的一组组件的配置信息的网络计算系统中的方法。为网络计算系统中的组件集合存储配置信息以形成存储的配置信息。在所描绘的示例中，组件可以是节点内的节点或设备。响应于电源循环获得当前配置。将当前配置信息与存储的配置信息进行比较以形成比较。如果比较中存在差异，则更新所存储的配置信息。存储的配置信息用于在发生电源周期时配置组件。

50. 发明授权

US08782024B2 Managing the sharing of logical resources among separate partitions of a logically partitioned computer system 失效
标题翻译：管理逻辑分区计算机系统的不同分区之间的逻辑资源共享
公开(公告)号：US08782024B2
公开(公告)日：2014-07-15
申请号：US10777724
申请日：2004-02-12
申请人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
发明人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
IPC分类号： G06F7/00
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/5077
摘要： A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.
摘要翻译：提供了一种用于在逻辑分区数据处理系统中的逻辑分区之间共享资源并且以这样的方式管理对资源的改变的机制，使得共享操作系统能够以优雅的方式处理各种转换。四个管理程序功能加上特定的返回代码管理一个分区所拥有的资源到另一个（客户端）分区的授权，客户端分区接受授予的资源，客户机分区返回授权资源，以及由所拥有的分区撤销访问。这四个虚拟机管理程序功能由拥有和客户机分区明确地调用，或者由管理程序自动地响应于分区终止而调用。管理程序功能提供所需的基础设施来管理分区之间逻辑资源的共享。

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