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41. 发明授权

US07009298B2 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层
公开(公告)号：US07009298B2
公开(公告)日：2006-03-07
申请号：US10639120
申请日：2003-08-11
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： H01L21/302
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.
摘要翻译：提供了一种接触结构，其结合使用四 - 二烷基酰氨基 - 钛，Ti（NMe 2 O 3）4 Si 3 O 4的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层。，作为前体。

42. 发明授权

US06995059B2 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 失效
公开(公告)号：US06995059B2
公开(公告)日：2006-02-07
申请号：US10627468
申请日：2003-07-25
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

43. 发明授权

US06917052B2 Modified contact for programmable devices 失效
标题翻译：修改了可编程器件的触点
公开(公告)号：US06917052B2
公开(公告)日：2005-07-12
申请号：US10864232
申请日：2004-06-09
申请人： Stephen J. Hudgens , Tyler A. Lowrey
发明人： Stephen J. Hudgens , Tyler A. Lowrey
IPC分类号： H01L23/525 , H01L45/00 , H01L47/00 , G11C11/50
CPC分类号： H01L23/5252 , H01L23/5256 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.
摘要翻译：在一方面，提供一种设置和重新编程可编程设备的状态的设备。在一方面，提供一种方法，使得通过暴露形成在基底上的接触的电介质形成开口。接触的电阻率通过将离子注入接触中的至少一种来修饰，在接触上沉积材料，以及处理与等离子体的接触。在一个方面，在开口内形成间隔件，并且在开口内和修改的接触件上形成可编程材料。导体形成在可编程材料上，触点传输到信号线。

44. 发明授权

US06795338B2 Memory having access devices using phase change material such as chalcogenide 有权
标题翻译：具有使用相变材料（例如硫族化物）的进入装置的存储器
公开(公告)号：US06795338B2
公开(公告)日：2004-09-21
申请号：US10319769
申请日：2002-12-13
申请人： Ward D. Parkinson , Tyler A. Lowrey
发明人： Ward D. Parkinson , Tyler A. Lowrey
IPC分类号： G11C1100
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/74 , G11C2213/76 , H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.
摘要翻译：简而言之，根据本发明的实施例，提供了一种存储器。存储器可以包括耦合到存储器元件的存储器元件和第一存取器件，其中第一存取器件包括第一硫族化物材料。存储器还可以包括耦合到第一接入设备的第二接入设备，其中第二接入设备包括第二硫族化物材料。

45. 发明授权

US06784046B2 Method of making vertical diode structures 失效
标题翻译：制造垂直二极管结构的方法
公开(公告)号：US06784046B2
公开(公告)日：2004-08-31
申请号：US10104240
申请日：2002-03-22
申请人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
发明人： Fernando Gonzalez , Tyler A. Lowrey , Trung Tri Doan , Raymond A. Turi , Graham R. Wolstenholme
IPC分类号： H01L218234
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L27/0814 , H01L27/101 , H01L27/1021 , H01L27/24 , H01L29/6609 , H01L29/66136 , H01L29/861 , H01L45/04 , H01L45/145 , Y10S257/903 , Y10S257/91 , Y10S438/979
摘要： A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
摘要翻译：提供了一种制造垂直二极管的方法，所述垂直二氧化物具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。硅化钛层覆盖二极管开口的内表面并接触有源区。二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。顶部由底部界定，以便不与硅化钛层接触。对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

46. 发明授权

US06764934B2 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random 失效
标题翻译：形成接触开口的半导体加工方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（电容）电路的方法
公开(公告)号：US06764934B2
公开(公告)日：2004-07-20
申请号：US10137100
申请日：2002-05-01
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H04L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

47. 发明授权

US06674115B2 Multiple layer phrase-change memory 有权
标题翻译：多层短语更改记忆
公开(公告)号：US06674115B2
公开(公告)日：2004-01-06
申请号：US10309633
申请日：2002-12-04
申请人： Stephen J. Hudgens , Tyler A. Lowrey , Patrick J. Klersy
发明人： Stephen J. Hudgens , Tyler A. Lowrey , Patrick J. Klersy
IPC分类号： H01L2976
CPC分类号： H01L45/06 , H01L29/8615 , H01L45/1233 , H01L45/128 , H01L45/144
摘要： A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.
摘要翻译：相变存储器可以形成有由阻挡层隔开的至少两个相变材料层。使用多个相变层能够减少编程体积，同时仍然提供足够的热绝缘。

48. 发明授权

US06586761B2 Phase change material memory device 有权
标题翻译：相变材料存储器件
公开(公告)号：US06586761B2
公开(公告)日：2003-07-01
申请号：US09948830
申请日：2001-09-07
申请人： Tyler A. Lowrey
发明人： Tyler A. Lowrey
IPC分类号： H01L4700
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/124 , H01L45/1293 , H01L45/144 , H01L45/1691
摘要： A phase change material memory cell may be formed with singulated, cup-shaped phase change material. The interior of the cup-shaped phase change material may be filled with a thermal insulating material. As a result, heat losses upwardly through the phase change material may be reduced and adhesion problems between the phase change material and the rest of the device may likewise be reduced in some embodiments. In addition, a barrier layer may be provided between the upper electrode and the remainder of the device that may reduce species incorporation from the top electrode into the phase change material, in some embodiments. Chemical mechanical planarization may be utilized to define the phase change material reducing the effects of phase change material dry etching in some embodiments.
摘要翻译：相变材料存储单元可以形成为单切形的杯形相变材料。杯状相变材料的内部可以填充绝热材料。结果，在一些实施例中，相变材料向上的热损失可能会降低，同相材料与器件的其余部分之间的粘合问题同样可以减少。此外，在一些实施例中，可以在上电极和器件的其余部分之间提供阻挡层，其可以减少从顶电极引入到相变材料中的物质。在一些实施方案中，化学机械平面化可用于限定相变材料减少相变材料干蚀刻的影响。

49. 发明授权

US06555860B2 Compositionally modified resistive electrode 有权
公开(公告)号：US06555860B2
公开(公告)日：2003-04-29
申请号：US09770968
申请日：2001-01-25
申请人： Tyler A. Lowrey , Stephen J. Hudgens , Patrick Klersy
发明人： Tyler A. Lowrey , Stephen J. Hudgens , Patrick Klersy
IPC分类号： H01L2972
CPC分类号： H01L29/685 , G11C13/0004 , H01L27/105 , H01L27/24
摘要： An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor. The electrode comprises a first portion having a first thermal coefficient of resistivity and a second portion having a different second thermal coefficient of resistivity. A method including modifying the thermal coefficient of resisting of a portion of an electrode.

50. 发明授权

US06329686B1 Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby 失效
标题翻译：通过采用成角度的侧壁注入和由此制造的半导体器件制造导电带以将触点互连到相应的数字线的方法
公开(公告)号：US06329686B1
公开(公告)日：2001-12-11
申请号：US09439623
申请日：1999-11-12
申请人： Tyler A. Lowrey , Shubneesh Batra
发明人： Tyler A. Lowrey , Shubneesh Batra
IPC分类号： H01L2972
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10814 , H01L27/10885 , H01L27/112
摘要： A method of interconnecting bit contacts to corresponding digit lines of a semiconductor memory device. The method is particularly useful for fabricating semiconductor memory devices having digit lines that are less than about 0.2 microns wide and spaced less than about 0.2 microns apart from one another. A mask, which shields portions of the digit lines of the semiconductor device, through which portions of the digit lines proximate the bit contacts are exposed, is disposed over the semiconductor device. The mask preferably includes elongated apertures alignable transversely to the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device. Thus, portions of the sidewall spacers of one side of each of the digit lines, sidewall spacers on the opposite sides of the digit lines, or the bit contacts may not be exposed to dopant. Doped oxide regions of the sidewall spacers may be removed with selectivity over undoped oxide regions or silicon nitride regions of the sidewall spacers. As the doped oxide regions are removed from the digit lines, a connect region of a conductive element of each of the digit lines is exposed. Conductive material may then be disposed adjacent the exposed connect region of the conductive element and in contact with the bit contact to establish an electrical link between the bit contact and its corresponding digit line. Semiconductor devices including such a conductive strap structure and, in particular, semiconductor devices which employ a conductive strap to interconnect a bit contact and a digit line having widths of less than about 0.2 microns and spaced less than about 0.2 microns apart from an adjacent digit line are also within the scope of the present invention.
摘要翻译：将位触点互连到半导体存储器件的相应数字线的方法。该方法特别适用于制造具有小于约0.2微米宽并且彼此间隔小于约0.2微米的数字线的半导体存储器件。屏蔽半导体器件的数字线的部分，靠近位触点的数位线的部分被暴露的掩模设置在半导体器件上。掩模优选地包括横向于数字线对准的细长孔。掺杂剂以与半导体器件的平面非垂直的角度指向半导体器件。因此，每个数字线的一侧，数字线的相对侧上的侧壁间隔物或位触点的部分侧壁间隔物可能不暴露于掺杂剂。可以在侧壁间隔物的未掺杂氧化物区域或氮化硅区域上选择性地去除侧壁间隔物的掺杂氧化物区域。随着从数字线移除掺杂氧化物区域，每个数字线的导电元件的连接区域被暴露。然后可以将导电材料设置在导电元件的暴露的连接区域附近并与位触点接触，以在位触点和其相应的数字线之间建立电连接。包括这种导电带结构的半导体器件，特别是采用导电带来互连位触点和数字线的半导体器件，其宽度小于约0.2微米，间隔小于约0.2微米，与相邻数字线也在本发明的范围内。

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