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41. 发明授权

US07303961B2 Method for producing a junction region between a trench and a semiconductor zone surrounding the trench 有权
标题翻译：用于在沟槽和围绕沟槽的半导体区域之间产生结区的方法
公开(公告)号：US07303961B2
公开(公告)日：2007-12-04
申请号：US11027496
申请日：2004-12-30
申请人： Hans Weber , Gerhard Silvester Neugschwandtner , Martin Poelzl
发明人： Hans Weber , Gerhard Silvester Neugschwandtner , Martin Poelzl
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier layer (15) to an upper part (O) of the inner walls of the trench (3), and production of a first oxide layer (7) on a lower part (U) of the inner walls, said lower part not being covered by the oxidation barrier layer (15), by means of thermal oxidation of the uncovered (U) part of the inner walls.
摘要翻译：在沟槽半导体器件（1）中，在沟槽（3）和围绕沟槽（3）的半导体区域（2）之间产生结区域（2,5,6,7）的方法具有以下步骤：应用氧化阻挡层（15）到所述沟槽（3）的内壁的上部（O），以及在所述内壁的下部（U）上产生第一氧化物层（7），所述下部不被氧化阻挡层（15）覆盖，通过内壁的未覆盖（U）部分的热氧化。

42. 发明授权

US08803230B2 Semiconductor transistor having trench contacts and method for forming therefor 有权
标题翻译：具有沟槽触点的半导体晶体管及其形成方法
公开(公告)号：US08803230B2
公开(公告)日：2014-08-12
申请号：US13350972
申请日：2012-01-16
申请人： Martin Poelzl , Georg Ehrentraut
发明人： Martin Poelzl , Georg Ehrentraut
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts.
摘要翻译：本文描述的实施例涉及具有沟槽接触的半导体晶体管，特别是涉及在栅电极下方具有场电极的半导体晶体管，以及用于制造具有沟槽接触的半导体晶体管的相关方法。

43. 发明申请

US20130181281A1 Semiconductor Transistor Having Trench Contacts and Method for Forming Therefor 有权
标题翻译：具有沟槽触点的半导体晶体管及其形成方法
公开(公告)号：US20130181281A1
公开(公告)日：2013-07-18
申请号：US13350972
申请日：2012-01-16
申请人： Martin Poelzl , Georg Ehrentraut
发明人： Martin Poelzl , Georg Ehrentraut
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： Embodiments described herein relate to semiconductor transistors having trench contacts, in particular to semiconductor transistors having a field electrode below a gate electrode, and to related methods for producing semiconductor transistors having trench contacts.
摘要翻译：本文描述的实施例涉及具有沟槽接触的半导体晶体管，特别是涉及在栅极下方具有场电极的半导体晶体管，以及用于制造具有沟槽接触的半导体晶体管的相关方法。

44. 发明申请

US20120315759A1 METHOD FOR PRODUCING CONTACT OPENINGS IN A SEMICONDUCTOR BODY AND SELF-ALIGNED CONTACT STRUCTURES ON A SEMICONDUCTOR BODY 有权
标题翻译：在半导体体中生产接触开口的方法和半导体体上的自对准接触结构
公开(公告)号：US20120315759A1
公开(公告)日：2012-12-13
申请号：US13560091
申请日：2012-07-27
申请人： Heimo Hofer , Martin Poelzl
发明人： Heimo Hofer , Martin Poelzl
IPC分类号： H01L21/28
CPC分类号： H01L29/7813 , H01L21/3086 , H01L21/31144 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/78642
摘要： Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
摘要翻译：通过在半导体主体的主表面上形成多个自对准结构，在半导体本体中产生接触开口，每个自对准结构填充形成在半导体本体中并在主表面上方并延伸到主表面上的沟槽。相邻的自对准结构具有彼此面对的间隔开的侧壁。间隔层形成在自对准结构的侧壁上。在相邻的自对准结构之间的半导体本体中形成开口，而间隔层位于自对准结构的侧壁上。每个开口具有对应于间隔层的厚度的相邻沟槽的侧壁的宽度和距离。自对准的接触结构也可以在具有或不使用间隔层的半导体本体上产生。

45. 发明申请

US20120184095A1 Method for Manufacturing a Semiconductor Device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120184095A1
公开(公告)日：2012-07-19
申请号：US13005694
申请日：2011-01-13
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/28
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供具有水平表面的半导体本体。在水平面上形成外延硬掩模。通过在水平表面上相对于外延硬掩模的选择性外延形成外延区域，使得外延区域被调整到外延硬掩模。在半导体本体中形成垂直沟槽。绝缘场板形成在垂直沟槽的下部，绝缘栅电极形成在绝缘场板的上方。此外，提供了一种用于形成场效应半导体器件的方法。

46. 发明申请

US20100055892A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20100055892A1
公开(公告)日：2010-03-04
申请号：US12200509
申请日：2008-08-28
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/3205
CPC分类号： H01L29/66666 , H01L21/28035 , H01L29/407 , H01L29/41766 , H01L29/66734 , H01L29/7813
摘要： A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
摘要翻译：一种形成半导体器件的方法。一个实施例提供了具有侧壁隔离的沟槽的半导体衬底。在沟槽的一部分中去除侧壁隔离。栅极电介质形成在铺设的敞开的侧壁上。与日期电介质相邻地形成栅电极。栅电极的上表面位于半导体衬底的表面下方的深度d1处。在栅电极上方去除栅极氧化物。在栅电极和半导体衬底上同时形成隔离，使得栅电极之间的隔离和半导体衬底之间的隔离之间的高度差d2的绝对值小于深度d1。

47. 发明授权

US07375029B2 Method for fabricating contact holes in a semiconductor body and a semiconductor structure 有权
标题翻译：在半导体本体和半导体结构中制造接触孔的方法
公开(公告)号：US07375029B2
公开(公告)日：2008-05-20
申请号：US11287500
申请日：2005-11-25
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/8242
CPC分类号： H01L29/66727 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66143 , H01L29/66348 , H01L29/66734
摘要： A method for fabricating contact holes in a semiconductor body proceeds from a structure in which: a plurality of trenches isolated from one another by mesa regions are provided in the semiconductor body, and electrodes are provided in the trenches, which electrodes are electrically insulated from the semiconductor body by a first insulation layer, and the upper ends of which electrodes are situated at a deeper level than the upper ends of the trenches. The method comprises the steps of: producing a second insulation layer by subjecting parts of the surface of the structure to a thermal oxidation process, and carrying out a planarization process in such a way that the semiconductor body is uncovered in the region of the mesa regions, and forming the contact holes in the mesa regions using the residues of the second insulation layer remaining after the planarization process as a contact hole mask.
摘要翻译：在半导体本体中制造接触孔的方法从半导体本体中设置有多个通过台面区隔开的沟槽的结构，并且在沟槽中设置电极，这些电极与半导体本体通过第一绝缘层，并且其上端的电极位于比沟槽的上端更深的水平。该方法包括以下步骤：通过使结构的表面的部分经受热氧化工艺，并且以这样的方式进行平坦化处理来制造第二绝缘层，使得半导体主体在台面区域的区域中未被覆盖并且使用在平坦化处理之后残留的第二绝缘层的残留物作为接触孔掩模，在台面区域中形成接触孔。

48. 发明申请

US20140167069A1 SYSTEMS AND METHODS FOR INTEGRATING BOOTSTRAP CIRCUIT ELEMENTS IN POWER TRANSISTORS AND OTHER DEVICES 有权
标题翻译：用于集成功率晶体管和其他器件中的引导电路元件的系统和方法
公开(公告)号：US20140167069A1
公开(公告)日：2014-06-19
申请号：US13718775
申请日：2012-12-18
申请人： Martin Vielemeyer , Sylvain Leomant , Milko Paolucci , Martin Poelzl
发明人： Martin Vielemeyer , Sylvain Leomant , Milko Paolucci , Martin Poelzl
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L21/38 , H01L21/385 , H01L21/8234 , H01L23/64 , H01L23/642 , H01L23/645 , H01L27/0676 , H01L27/0705 , H01L27/0711 , H01L2924/0002 , H03K17/6871 , H01L2924/00
摘要： Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.
摘要翻译：实施例涉及与诸如功率晶体管或其它半导体器件的至少一个其它器件集成的自举电路。在实施例中，自举电路可以包括自举电容器和自举二极管，或者自举电路可以包括自举电容器和自举晶体管。在实施例中，自举电容器包括与电解，陶瓷或其它电容器相对的基于半导体的电容器。在一个实施例中，自举电路与另一电路或器件（例如功率晶体管器件）的集成在实施例中处于硅级，而不是作为常规方法的模块化系统级封装。换句话说，在实施例中，自举电路元件和功率晶体管或其它器件的组合形成硅系统或集成电路，并且另外可以被布置在单个封装中。

49. 发明授权

US08642459B2 Method for forming a semiconductor device with an isolation region on a gate electrode 有权
标题翻译：在栅电极上形成具有隔离区域的半导体器件的方法
公开(公告)号：US08642459B2
公开(公告)日：2014-02-04
申请号：US12200509
申请日：2008-08-28
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/3205
CPC分类号： H01L29/66666 , H01L21/28035 , H01L29/407 , H01L29/41766 , H01L29/66734 , H01L29/7813
摘要： A method for forming a semiconductor device. One embodiment provides a semiconductor substrate having a trench with a sidewall isolation. The sidewall isolation is removed in a portion of the trench. A gate dielectric is formed on the laid open sidewall. A gate electrode is formed adjacent to the date dielectric. The upper surface of the gate electrode is located at a depth d1 below the surface of the semiconductor substrate. The gate oxide is removed above the gate electrode. An isolation is formed simultaneously on the gate electrode and the semiconductor substrate such that the absolute value of height difference d2 between the isolation over the gate electrode and the isolation over the semiconductor substrate is smaller than the depth d1.
摘要翻译：一种形成半导体器件的方法。一个实施例提供了具有侧壁隔离的沟槽的半导体衬底。在沟槽的一部分中去除侧壁隔离。栅极电介质形成在铺设的敞开的侧壁上。与日期电介质相邻地形成栅电极。栅电极的上表面位于半导体衬底的表面下方的深度d1处。在栅电极上方去除栅极氧化物。在栅电极和半导体衬底上同时形成隔离，使得栅电极之间的隔离和半导体衬底之间的隔离之间的高度差d2的绝对值小于深度d1。

50. 发明授权

US08637367B2 Method for producing an insulation layer between two electrodes 有权
标题翻译：用于在两个电极之间制造绝缘层的方法
公开(公告)号：US08637367B2
公开(公告)日：2014-01-28
申请号：US13207056
申请日：2011-08-10
申请人： Martin Poelzl
发明人： Martin Poelzl
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： Method for producing an insulation layer between a first electrode and a second electrode in a trench of a semiconductor body, wherein the method comprises the following features: providing a semiconductor body with a trench formed therein, wherein a first electrode is formed in a lower part of the trench, producing an insulation layer on the first electrode and at the sidewalls of the trench in an upper part of the trench in such a way that the insulation layer is formed in a U-shaped fashion in the trench, producing a protective layer on the insulation layer at least at the bottom of the remaining void in the trench, removing the insulation layer at the sidewalls of the trench in the upper part of the trench, removing the protective layer, producing a second electrode at least on the insulation layer above the first electrode.
摘要翻译：一种在半导体主体的沟槽中的第一电极和第二电极之间制造绝缘层的方法，其中所述方法包括以下特征：提供半导体本体，其中形成有沟槽，其中第一电极形成在下部在沟槽的上部的第一电极和沟槽的侧壁处产生绝缘层，使得绝缘层在沟槽中形成为U形形式，从而产生保护层至少在沟槽中的剩余空隙的底部的绝缘层上，去除沟槽上部沟槽侧壁处的绝缘层，去除保护层，至少在绝缘层上产生第二电极在第一电极之上。

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