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41. 发明申请

US20090026542A1 INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR ASSEMBLY IN THIN-SOI TECHNOLOGY 有权
标题翻译：集成电路，包括半导体器件在薄SOI技术中的集成电路
公开(公告)号：US20090026542A1
公开(公告)日：2009-01-29
申请号：US11829264
申请日：2007-07-27
申请人： Uwe Wahl
发明人： Uwe Wahl
IPC分类号： H01L29/735 , H01L21/331 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0251
摘要： An integrated circuit including a semiconductor assembly in thin-film SOI technology is disclosed. One embodiment provides a semiconductor assembly in thin-film SOI technology including a first semiconductor substrate structure of a second conductivity type inverse to a first conductivity type in a semiconductor substrate below a first semiconductor layer, a second semiconductor substrate structure of a second conductivity type in a semiconductor substrate below a second semiconductor layer structure, and a third semiconductor substrate structure of the first conductivity type below the first semiconductor layer structure in the semiconductor substrate and otherwise surrounded by the first semiconductor substrate structure.
摘要翻译：公开了一种包括薄膜SOI技术中的半导体组件的集成电路。一个实施例提供一种薄膜SOI技术中的半导体组件，包括在第一半导体层下面的半导体衬底中与第一导电类型相反的第二导电类型的第一半导体衬底结构，第二导电类型的第二半导体衬底结构在第二半导体层结构之下的半导体衬底，以及第一导电类型的第三半导体衬底结构，在第一半导体衬底的第一半导体层结构之下，由第一半导体衬底结构包围。

42. 发明授权

US07332788B2 Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it 有权
标题翻译：具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法
公开(公告)号：US07332788B2
公开(公告)日：2008-02-19
申请号：US10927270
申请日：2004-08-26
申请人： Dirk Ahlers , Miguel Cuadron Marion , Uwe Wahl , Armin Willmeroth
发明人： Dirk Ahlers , Miguel Cuadron Marion , Uwe Wahl , Armin Willmeroth
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L27/0883 , H01L29/0634 , H01L29/0646 , H01L29/66712
摘要： The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complimentarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complimentarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).
摘要翻译：本发明涉及具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法。在该半导体功率器件的情况下，在芯片体积整体上配置垂直配置并与半导体芯片体积（5）相辅相成的电荷补偿单元（27）的区域（6），补充掺杂区域（6）延伸到半导体功率元件（7）的表面区域（11）中，并且不突出到半导体表面元件（1）的表面区域（12）中。

43. 发明申请

US20050045922A1 Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it 有权
标题翻译：具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法
公开(公告)号：US20050045922A1
公开(公告)日：2005-03-03
申请号：US10927270
申请日：2004-08-26
申请人： Dirk Ahlers , Miguel Marion , Uwe Wahl , Armin Willmeroth
发明人： Dirk Ahlers , Miguel Marion , Uwe Wahl , Armin Willmeroth
IPC分类号： H01L21/336 , H01L27/088 , H01L29/06 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7802 , H01L27/0883 , H01L29/0634 , H01L29/0646 , H01L29/66712
摘要： The invention relates to a semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it. In the case of this semiconductor power device, zones (6) in charge compensation cells (27) that are arranged vertically and doped complementarily to the semiconductor chip volume (5) are arranged in the entire chip volume, the complementarily doped zones (6) extending right into surface regions (11) of the semiconductor power elements (7) and not projecting into surface regions (12) of semiconductor surface elements (1).
摘要翻译：本发明涉及具有电荷补偿结构和单片集成电路的半导体功率器件及其制造方法。在该半导体功率器件的情况下，在整个芯片体积上配置垂直配置并与半导体芯片体积（5）互补配置的电荷补偿单元（27）中的区域（6），互补掺杂区域（6）延伸到半导体功率元件（7）的表面区域（11）中，并且不突出到半导体表面元件（1）的表面区域（12）中。

44. 发明授权

US06693011B2 Power MOS element and method for producing the same 有权
标题翻译：功率MOS元件及其制造方法
公开(公告)号：US06693011B2
公开(公告)日：2004-02-17
申请号：US10225022
申请日：2002-08-21
申请人： Uwe Wahl , Holger Vogt
发明人： Uwe Wahl , Holger Vogt
IPC分类号： H01L21336
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66727 , H01L29/7813
摘要： A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench. For producing, three photolithographic steps are sufficient, which serve to etch said gate trenches and said connecting gate trench, to produce said contact holes for said source region and said channel region as well as for said connecting gate trench, and to finally structure said gate contacts and said source contact. Thus, a flexible layout concept is possible in which said gate contact can also be placed in the middle of or at another location on said power MOS element without additional expenditure. Optionally, without additional process steps, margin terminating structures can be produced parallel to the formation of said active transistor region in the form of circumferential floating rings or of floating field plates.
摘要翻译：功率MOS元件包括具有第一掺杂类型的掺杂的漂移区域，具有与所述第一掺杂类型互补且与所述沟道区域和所述漂移区域相邻的第二掺杂类型的掺杂的沟道区域，以及源极区域，具有所述第一掺杂类型的掺杂，所述源极区域与所述沟道区域相邻。此外，所述功率MOS元件包括延伸到所述漂移区并且包括通过绝缘体与晶体管区域绝缘的导电材料的多个基本上平行的栅极沟槽。各个栅极沟槽通过连接栅极沟槽连接，栅极触点仅通过所述连接栅极沟槽中的接触孔以导电的方式连接到有源栅极沟槽。为了制造，三个光刻步骤是足够的，其用于蚀刻所述栅极沟槽和所述连接栅极沟槽，以产生用于所述源极区域和所述沟道区域以及所述连接栅极沟槽的所述接触孔，并且最终构造所述栅极联系人和来源联系人。因此，灵活的布局概念是可能的，其中所述栅极接触也可以放置在所述功率MOS元件的中间或另一位置，而不需要额外的费用。任选地，在没有额外的工艺步骤的情况下，边缘端接结构可以平行于周向浮动环或浮动场板形式的所述有源晶体管区域的形成。

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