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41. 发明申请

WO1980001966A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1980001966A1
公开(公告)日：1980-09-18
申请号：PCT/JP1980000036
申请日：1980-02-29
申请人： FUJITSU LTD , HIRANO Y
发明人： FUJITSU LTD
IPC分类号： H01L23/12
CPC分类号： H01L24/85 , H01L23/057 , H01L23/495 , H01L23/49562 , H01L23/49582 , H01L23/66 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/04042 , H01L2224/0603 , H01L2224/29111 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48175 , H01L2224/48227 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/8319 , H01L2224/8385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01031 , H01L2924/01042 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/12032 , H01L2924/1306 , H01L2924/15153 , H01L2924/1517 , H01L2924/15787 , H01L2924/1579 , H01L2224/78 , H01L2924/00 , H01L2924/01033 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： PCT No. PCT/JP80/00036 Sec. 371 Date Nov. 9, 1980 Sec. 102(e) Date Oct. 31, 1980 PCT Filed Feb. 29, 1980 PCT Pub. No. WO80/01966 PCT Pub. Date Sep. 18, 1980.A semiconductor device wherein a semiconductor element is bonded with brazing material on a metalized layer formed on an insulating substrate, with lead wires being used to connect the electrodes of the semiconductor element to the metalized layer. An element bonding area and lead wire connecting areas are provided on the metalized layer and are separated, at the inside of an aperture provided in a sealing member which seals the semiconductor element, by separation regions. Therefore, the brazing material used for securing the semiconductor element to the metalized layer does not flow up to the lead wire connecting areas, thus improving the manufacturing yield and reliability of the semiconductor device.
摘要翻译： PCT No.PCT / JP80 / 00036 Sec。 371日期1980年11月9日 102（e）日期1980年10月31日PCT提交1980年2月29日PCT公布。出版物WO80 / 01966 日期：1980年9月18日。半导体器件，其中半导体元件与形成在绝缘基板上的金属化层上的钎焊材料接合，其中引线用于将半导体元件的电极连接到金属化层。元件接合区域和引线连接区域设置在金属化层上，并且在设置在通过分离区域密封半导体元件的密封构件的孔的内侧分离。因此，用于将半导体元件固定到金属化层的钎焊材料不会流到引线连接区域，从而提高了半导体器件的制造成品率和可靠性。

42. 发明申请

WO1980001859A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND WIRING METHOD THEREFOR 审中-公开
标题翻译：半导体集成电路及其布线方法
公开(公告)号：WO1980001859A1
公开(公告)日：1980-09-04
申请号：PCT/JP1980000025
申请日：1980-02-22
申请人： FUJITSU LTD , BABA S , SATO S , KIKUCHI H
发明人： FUJITSU LTD
IPC分类号： H01L21/82
CPC分类号： H03K19/1735 , G06F17/5077 , H01L27/0207
摘要： A large scale integrated circuit and a wiring method therefore, wherein use is made of a grid method which comprises partitioning a layout space into a lattice pattern by vertical and horizontal lines which are spaced apart by a distance which is greater than a length corresponding to a minimum dimension that can be patterned by a manufacturing process, drawing wire routing patterns onto the vertical and horizontal lines for interconnection among layout unit cells, and then forming wires according to the wire routing patterns. The spacing distance (d) of vertical and horizontal lines in grid (10) is designed to be shorter than wiring pitches on multi-wiring layers, i.e., to have a length of the greatest common measure to the minimum wiring pitch in each wiring layer. Onto the vertical and horizontal lines, which have the same spacing distance as above-mentioned, are drawn vertical and horizontal wire routing patterns (3, 4, 5). Since the longitudinal and lateral lengths of each cell are integral multiples of the spacing distance (d) in grid (10), terminals of each cell are positioned within a tolerable range for wiring.

43. 发明申请

WO1980001222A1 METHOD OF MANUFACTURING SEMICONDUCTOR LASER DEVICES 审中-公开
标题翻译：制造半导体激光器件的方法
公开(公告)号：WO1980001222A1
公开(公告)日：1980-06-12
申请号：PCT/JP1979000302
申请日：1979-11-28
申请人： FUJITSU LTD , FUJIWARA K
发明人： FUJITSU LTD
IPC分类号： H01L21/58
CPC分类号： H01L33/642 , H01L23/3732 , H01L24/45 , H01L24/48 , H01L33/641 , H01L2224/45144 , H01L2224/48091 , H01L2224/48472 , H01L2924/01322 , H01L2924/12042 , H01S5/02208 , H01S5/02484 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing semiconductor laser devices utilized in various kinds of communication systems. In the course of realizing semiconductor laser devices having a construction in which a heat sink (23) made of diamond or the like is placed on a heat radiating stud (21) which is a part of a sealed container for a semiconductor laser element (21), with the semiconductor laser element (21) being disposed on the heat sink (23), the method of manufacturing the laser device comprises the following steps: providing a layer of gold alloy (36) on the surface of the heat sink (23), placing the semiconductor laser element (24) on the layer of gold alloy (36) at a temperature below the eutectic point, heating the entire device at a temperature above the eutectic point, and cooling it thereby fixing the semiconductor laser element (24) onto the heat sink (23). The semiconductor laser devices manufactured by this method have a long life.

44. 发明申请

WO1982001798A1 SYSTEM FOR READING VARIABLE SCANNING PICTURE SIGNAL WHILE MOVING THRESHOLD LEVEL 审中-公开
标题翻译：用于在移动阈值电平时读取可变扫描图像信号的系统
公开(公告)号：WO1982001798A1
公开(公告)日：1982-05-27
申请号：PCT/JP1981000329
申请日：1981-11-11
申请人： FUJITSU LTD , AMEMIYA TAKESHI
发明人： FUJITSU LTD
IPC分类号： H04N01/17
CPC分类号： H04N1/415 , H04N1/403
摘要： Systeme de lecture de signaux d'images avec 'sous-scanner' pas a pas, lorsque le temps de transmission pour une ligne est court, dans un equipement a fac-similer qui lit des informations d'images tout en deplacant un original (1). Lorsque l'information d'image est lue tout en deplacant l'original (1), la quantite de charges stockees dans un detecteur d'image (6) devient insuffisante. Lorsque le signal d'image est identifie a un niveau de seuil fixe TH, une erreur se produit dans la lecture. De maniere a eliminer ce probleme, un circuit de commande du niveau du seuil (14) est prevu pour deplacer le niveau de seuil en reponse au temps de transmission pour une ligne divisee en blocs. Lorsque le temps de transmission pour le signal d'image dans une ligne ainsi lue est court, le niveau de seuil de l'exploration suivante est releve, et lorsqu'il est long, le niveau de seuil de l'exploration suivante est rabaisse.

45. 发明申请

WO1981001892A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：WO1981001892A1
公开(公告)日：1981-07-09
申请号：PCT/JP1980000333
申请日：1980-12-27
申请人： FUJITSU LTD , UCHIDA K , OKAMOTO T
发明人： FUJITSU LTD
IPC分类号： G06F15/16
CPC分类号： G06F9/3889 , G06F9/30036 , G06F9/3836 , G06F9/3859 , G06F9/3877 , G06F9/3887 , G06F15/8061
摘要： An information processing system (10) including an arithmetic unit (13) in which an item of data is processed according to one instruction, another arithmetic unit (14) in which plural items of data are processed according to one instruction, an instruction control unit (15) for distributing corresponding instruction groups to respective ones of the arithmetic units (13, 14), and a main memory (12) for exchanging data with the instruction control unit (15) and with both arithmetic units (13, 14). In the information processing system (10), a group of instructions among the above-mentioned groups of instructions, which group is restricted by the order of priority as to the execution sequence thereof, is synchronized by specially inserting a synchronization instruction (WAIT). It is also possible to divide the above-mentioned groups of instructions into a group of instructions to be serial-processed and a group of instructions capable of being parallel-processed, as to the execution sequence thereof, by inserting a serialization-start instruction (POST) and a serialization-release instruction (SUB - WAIT).

46. 发明申请

WO1981001685A1 INK RIBBON FOLDING MECHANISM FOR TYPEWRITER 审中-公开
标题翻译： INK RIBBON折叠机构TYPEWRITER
公开(公告)号：WO1981001685A1
公开(公告)日：1981-06-25
申请号：PCT/JP1980000304
申请日：1980-12-11
申请人： FUJITSU LTD , FUDATSUJI T , IMAGI T , MIURA H
发明人： FUJITSU LTD
IPC分类号： B41J32/02
CPC分类号： B41J32/02 , B41J33/10
摘要： An ink ribbon folding mechanism for a typewriter which is constructed to accomodate an endless ink ribbon (3) folded via a pair of feed rollers (4, 4'; 4A, 4A') in a ribbon case (6). In order to realize the smooth folding of the ink ribbon irrespective of the roughness of the ink ribbon surface (12) to be impacted by a type head, the contact point (17) of the feed rollers is displaced toward the smooth ribbon surface (13), which is not struck by the type head, with respect to the center (18) of the ribbon case, whereby the ink ribbon, when it is folded toward the smooth surface side, reaches the side wall (6a) of the ribbon case.

47. 发明申请

WO1981001484A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO1981001484A1
公开(公告)日：1981-05-28
申请号：PCT/JP1980000276
申请日：1980-11-06
申请人： FUJITSU LTD , MAEDA K
发明人： FUJITSU LTD
IPC分类号： H01L27/10
CPC分类号： G11C16/0441 , H01L23/522 , H01L27/115 , H01L29/78 , H01L29/7885 , H01L2924/0002 , H03K3/356008 , H01L2924/00
摘要： A semiconductor memory device composed of double gate-type field effect transistors, each of which has a control gate (25), and a floating gate (23) that stores electric charges. The semiconductor memory device requires an arrangement of reciprocal structures, namely a structure adapted to inject charges into the floating gate of the memory device, and a structure adapted to read-out the stored information. To this end, the device employs an injection-only transistor (TrW) with a structure adapted for charge-injection and a read-only transistor (TrR) with a structure adapted for reading, the floating gates (23) of both the transistors being electrically coupled to each other, the control gates (25) thereof being connected to a first common signal-wire, the drains (22W, 22R) thereof being connected to second-and third- different signalwires, respectively, and the sources (21W, 21R) thereof being grounded.

48. 发明申请

WO1981000474A1 COMPUTER PIPE LINE CONTROL SYSTEM 审中-公开
标题翻译：电脑管线控制系统
公开(公告)号：WO1981000474A1
公开(公告)日：1981-02-19
申请号：PCT/JP1980000171
申请日：1980-07-25
申请人： FUJITSU LTD , MIZUSHIMA Y
发明人： FUJITSU LTD
IPC分类号： G06F09/38
CPC分类号： G06F9/381 , G06F9/28 , G06F9/3869
摘要： A computer pipe line control system wherein, for the purpose of repeatedly executing a process flow based on the same operation command, given tags are stored in plural tag registers in the first information executing step and, in the second and sequential steps in which the same instructions are repeated, desired tags are selected from the tags stored in the tag registers, so that the execution is started from the second phase with no execution of the first phase.

49. 发明申请

WO1980002889A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO1980002889A1
公开(公告)日：1980-12-24
申请号：PCT/JP1980000132
申请日：1980-06-14
申请人： FUJITSU LTD , TATEMATSU T
发明人： FUJITSU LTD
IPC分类号： G11C29/00
CPC分类号： G11C29/846
摘要： A memory device (10) including a conventional redundant memory array (12). The redundant memory array (12) is used for compensating the data stored in a defective memory cell (13') of a main memory-cell group (11) located in the memory device (10). Addressing means (15) for addressing one cell in the memory-cell group accesses both the main memory-cell group (11) and the redundant memory array (12). Simultaneously, operated are both detecting means (16), which detect whether address information AI to be supplied to the addressing means (15) addressed the defective memory cell (13') or not, and switching means (17) which selects either channel of the main memory-cell group (11) or of the redundant memory array (12) according to the result of the detecting means (16). The switching means (17) is connected between a main data bus (DBm) cooperating with the main memory-cell group (11) and a redundant data bus (DBr) cooperating with the redundant memory array (12).

50. 发明申请

WO1980002633A1 HOLLOW MULTILAYER PRINTED WIRING BOARD,AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：中空多层印刷布线板及其制造方法
公开(公告)号：WO1980002633A1
公开(公告)日：1980-11-27
申请号：PCT/JP1980000111
申请日：1980-05-23
申请人： FUJITSU LTD , KUROSAWA K , MIYAGAWA K , MITSUI H , MIYABARA A , YAMASHITA M , YAMAMOTO K , IMURA T
发明人： FUJITSU LTD
IPC分类号： H05K03/46
CPC分类号： H05K3/462 , H05K1/0272 , H05K1/053 , H05K3/426 , H05K3/427 , H05K3/429 , H05K3/4623 , H05K2201/0379 , H05K2201/09536 , H05K2201/096 , H05K2203/0315 , Y10T29/49126
摘要： The hollow multilayer printed wiring board is composed of plural print boards (1), (2), (3), (4) laminated with a predetermined spacing therebetween, each of which has a signal-conducting pattern (6) formed on at least one surface thereof and a land-conducting pattern (7) formed on at least one surface thereof. The board has through-holes (10) which are plated to connect with the land-conducting pattern and each of the through-holes and a plated through-hole in at least one board of the boards adjacent thereto are positioned on a straight line so as to provide a plated through-hole or an interstitial wire hole (12), (13). Formed on at least the upper- and lower- end surfaces of each through-hole (10) are low melting-point metal layers which function as conductors among the signal conducting patterns in 2 or more of the plural boards and as layer-bonding materials for the plural boards. The laminated boards, except at least one of the outer sides, is made of a heat-proof organic plastics-sheet or an insulated metal.

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