专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20170192780A1 Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements 审中-公开
公开(公告)号：US20170192780A1
公开(公告)日：2017-07-06
申请号：US14984078
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.

42. 发明申请

US20120185670A1 SCALAR INTEGER INSTRUCTIONS CAPABLE OF EXECUTION WITH THREE REGISTERS 审中-公开
标题翻译：标准整数指令可执行三个注册
公开(公告)号：US20120185670A1
公开(公告)日：2012-07-19
申请号：US13007050
申请日：2011-01-14
申请人： Bret L. Toll , Robert Valentine , Maxim Locktyukhin , Elmoustapha Ould-Ahmed-Vall
发明人： Bret L. Toll , Robert Valentine , Maxim Locktyukhin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30036 , G06F9/3012 , G06F9/3016 , G06F9/30185
摘要： A processing core implemented on a semiconductor chip is described. The processing core includes logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers, where, in the case of two registers input operand information is destroyed in one of two registers, and, in the case of three registers input operand is not destroyed. The processing core also includes steering circuitry coupled to the logic circuitry. The steering circuitry is to control first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from the scalar register bank if two register execution is identified for the scalar integer instructions or three registers are accessed from the scalar integer register bank if three register execution is identified for the scalar integer instructions. The steering circuitry is also to control second data paths between vector execution units and a vector register bank such that two registers are accessed from the vector register bank if two register execution is identified for the vector instructions or three registers are accessed from the vector register bank if three register execution is identified for the vector instructions.
摘要翻译：描述了在半导体芯片上实现的处理核心。处理核心包括用于识别矢量指令和整数标量指令是否要用两个寄存器或三个寄存器执行的逻辑电路，其中在两个寄存器的情况下输入操作数信息在两个寄存器之一中被销毁，并且在这种情况下的三个寄存器输入操作数不会被破坏。处理核心还包括耦合到逻辑电路的转向电路。转向电路是控制标量整数执行单元和标量整数寄存器组之间的第一数据路径，以便如果为标量整数指令识别两个寄存器执行，则从标量寄存器组访问两个寄存器，或者从标量访问三个寄存器整数寄存器组如果为标量整数指令标识了三个寄存器执行。转向电路还用于控制向量执行单元和向量寄存器组之间的第二数据路径，使得如果为向量指令识别了两个寄存器执行，则从向量寄存器组访问两个寄存器，或者从向量寄存器组访问三个寄存器如果为向量指令识别了三个寄存器执行。

43. 发明申请

US20150039851A1 METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY 有权
标题翻译：方法，装置，说明和逻辑提供矢量子字节分解功能
公开(公告)号：US20150039851A1
公开(公告)日：2015-02-05
申请号：US13956347
申请日：2013-07-31
申请人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Thomas Willhalm , Robert Valentine
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Thomas Willhalm , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/3889
摘要： Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into the least significant portion of a first vector element, and a third and fourth byte into the most significant portion. Processing continues shuffling a fifth and sixth byte into the least significant portion of a second vector element, and a seventh and eighth byte into the most significant portion. Then by shifting the first vector element by a first shift count and the second vector element by a second shift count, sub-byte elements are aligned to the least significant bits of their respective bytes. Processors then shuffle a byte from each of the shifted vector elements' least significant portions into byte positions of a destination vector element, and from each of the shifted vector elements' most significant portions into byte positions of another destination vector element.
摘要翻译：方法，装置，指令和逻辑提供SIMD矢量子字节解压缩功能。实施例包括将第一和第二字节混洗到第一向量元素的最低有效部分中，以及将第三和第四字节混入最重要部分。处理继续将第五和第六字节洗牌到第二向量元素的最低有效部分，并将第七和第八字节重新排列到最高有效部分。然后，通过将第一移位计数和第二向量元素移位第二移位计数，将子字节元素与它们各自的字节的最低有效位对齐。然后，处理器将来自移位向量元素的最小有效部分的每一个的字节从目的地向量元素的字节位置以及从每个移位向量元素的最高有效部分转移到另一目的地向量元素的字节位置。

44. 发明申请

US20140122831A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR COMPRESS AND ROTATE FUNCTIONALITY 有权
标题翻译：指令和逻辑提供向量压缩和旋转功能
公开(公告)号：US20140122831A1
公开(公告)日：2014-05-01
申请号：US13664401
申请日：2012-10-30
申请人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Robert Valentine
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Robert Valentine
IPC分类号： G06F15/80
CPC分类号： G06F15/8076 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30101 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30185 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F12/0811 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/62
摘要： Instructions and logic provide vector compress and rotate functionality. Some embodiments, responsive to an instruction specifying: a vector source, a mask, a vector destination and destination offset, read the mask, and copy corresponding unmasked vector elements from the vector source to adjacent sequential locations in the vector destination, starting at the vector destination offset location. In some embodiments, the unmasked vector elements from the vector source are copied to adjacent sequential element locations modulo the total number of element locations in the vector destination. In some alternative embodiments, copying stops whenever the vector destination is full, and upon copying an unmasked vector element from the vector source to an adjacent sequential element location in the vector destination, the value of a corresponding field in the mask is changed to a masked value. Alternative embodiments zero elements of the vector destination, in which no element from the vector source is copied.
摘要翻译：说明和逻辑提供矢量压缩和旋转功能。一些实施例，响应于指定向量源，掩码，向量目的地和目的地偏移的指令，读取掩码，并将向量源中的相应未屏蔽向量元素复制到向量目的地中的相邻顺序位置，从向量开始目的地偏移位置。在一些实施例中，来自向量源的未屏蔽向量元素被复制到向量目的地中的元素位置的总数的相邻顺序元素位置。在一些备选实施例中，只要向量目的地已满，复制就停止，并且在将未屏蔽向量元素从向量源复制到向量目的地中的相邻顺序元素位置时，掩码中相应字段的值被改变为被掩码值。替代实施例的向量目的地的零元素，其中没有复制来自向量源的元素。

45. 发明授权

US09632980B2 Apparatus and method of mask permute instructions 有权
公开(公告)号：US09632980B2
公开(公告)日：2017-04-25
申请号：US13976435
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Suleyman Sair
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Suleyman Sair
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F15/8092
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

46. 发明申请

US20140149802A1 Apparatus And Method To Obtain Information Regarding Suppressed Faults 有权
标题翻译：获取关于抑制故障信息的装置和方法
公开(公告)号：US20140149802A1
公开(公告)日：2014-05-29
申请号：US13688544
申请日：2012-11-29
申请人： Christopher J. Hughes , Jesus Corbal , Mark J. Charney , Milind B. Girkar , Elmoustapha Ould-Ahmed-Vall , Robert Valentine
发明人： Christopher J. Hughes , Jesus Corbal , Mark J. Charney , Milind B. Girkar , Elmoustapha Ould-Ahmed-Vall , Robert Valentine
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G06F9/30036 , G06F9/3851 , G06F9/3855 , G06F9/3865 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772
摘要： A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.
摘要翻译：处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。其他实施例被描述为所要求保护的。

47. 发明申请

US20190102184A1 APPARATUS AND METHOD FOR SHIFTING QUADWORDS AND EXTRACTING PACKED WORDS 审中-公开
公开(公告)号：US20190102184A1
公开(公告)日：2019-04-04
申请号：US15721466
申请日：2017-09-29
申请人： Venkateswara Madduri , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Mark Charney , Robert Valentine , Binwei Yang
发明人： Venkateswara Madduri , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Mark Charney , Robert Valentine , Binwei Yang
IPC分类号： G06F9/30
摘要： An apparatus and method for performing right-shifting operations on packed quadword data. For example, one embodiment of a processor comprises: a decoder to decode a right-shift instruction to generate a decoded right-shift instruction; a first source register to store a plurality of packed quadwords data elements; execution circuitry to execute the decoded right-shift instruction, the execution circuitry comprising shift circuitry to right-shift at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords; the execution circuitry to cause selection of 16 most significant bits of the first and second right-shifted quadwords to be written to 16 least significant bit regions of first and second quadword data element locations, respectively, of a destination register; and the destination register to store the specified set of the 16 most significant bits of the first and second right-shifted quadwords.

48. 发明申请

US20140189308A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY 有权
标题翻译：方法，装置，说明和逻辑提供矢量地址冲突检测功能
公开(公告)号：US20140189308A1
公开(公告)日：2014-07-03
申请号：US13731006
申请日：2012-12-29
申请人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
发明人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F9/30145 , G06F9/30185 , G06F9/3838 , G06F9/3887
摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突检测功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移量与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移，并且在目标寄存器中的相应冲突掩码中，设置对应于较少具有匹配偏移的重要数据字段。向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

49. 发明申请

US20140189307A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT RESOLUTION WITH VECTOR POPULATION COUNT FUNCTIONALITY 有权
标题翻译：方法，设备，说明和逻辑提供向量地址冲突分解与向量人口计数功能
公开(公告)号：US20140189307A1
公开(公告)日：2014-07-03
申请号：US13731005
申请日：2012-12-29
申请人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
发明人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F7/607 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3836 , G06F9/3887 , H03M7/20
摘要： Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

50. 发明申请

US20130290672A1 APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS 有权
标题翻译：遮罩说明书的装置和方法
公开(公告)号：US20130290672A1
公开(公告)日：2013-10-31
申请号：US13976435
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Suleyman Sair
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Suleyman Sair
IPC分类号： G06F15/80
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F15/8092
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
摘要翻译：描述了具有指令执行逻辑电路的装置。指令执行逻辑电路具有输入向量元素路由电路，以对三个不同的指令中的每一个执行以下操作：对于多个输出向量元素位置中的每一个，将输入向量元素从多个可用于输出输出向量元素的输入向量元素位置。输出向量元素和每个输入向量元素位置是三个不同指令的三个可用位宽之一。该装置还包括耦合到输入向量元素路由电路以屏蔽由输入向量路由选择元件电路产生的数据结构的掩蔽层电路。掩蔽层电路被设计为以与三个可用位宽对应的三个不同的粒度级别进行掩蔽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式