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41. 发明授权

US4072976A Gate protection device for MOS circuits 失效
标题翻译： MOS电路的栅极保护装置
公开(公告)号：US4072976A
公开(公告)日：1978-02-07
申请号：US754932
申请日：1976-12-28
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： H01L27/02 , H01L29/423 , H01L29/78 , H01L29/94
CPC分类号： H01L29/4232 , H01L27/0251 , H01L29/78 , H01L29/94 , Y10S148/055
摘要： The specification describes an integrated device for the input protection of MOS circuits. It consists of an MOS capacitor formed by the thinning of a section of the input gate dielectric, SiO.sub.2, and the thinning of an adjoining section of the gate metal, Al. An incoming pulse of static charge with high amplitude and short duration will break down the thinned dielectric of the capacitor before breaking down the relatively thick portion of the gate dielectric. Since the metal over the thin dielectric is also relatively thin, it evaporates from the vicinity of the fault by the generated Joule heat immediately following the breakdown. Thus, the breakdown is self healed and can be repeated many times without damaging the circuit.
摘要翻译：该规范描述了用于MOS电路的输入保护的集成器件。它由通过输入栅极电介质的一部分薄化而形成的MOS电容器，以及栅极金属Al的邻接部分的薄化。具有高幅度和短持续时间的静电荷的输入脉冲将在分解栅极电介质的较厚部分之前分解电容器的变薄的电介质。由于薄电介质上的金属也相对较薄，所以在故障附近之后立即从故障附近由产生的焦耳热蒸发掉。因此，故障是自我愈合的，并且可以重复多次而不损坏电路。

42. 发明申请

US20130111113A1 NAND Flash Memory Controller Exporting a NAND Interface 审中-公开
标题翻译： NAND闪存控制器导出NAND接口
公开(公告)号：US20130111113A1
公开(公告)日：2013-05-02
申请号：US13596926
申请日：2012-08-28
申请人： Eliyahou Harari , Richard R. Heye , Robert D. Selinger , Menahem Lasser
发明人： Eliyahou Harari , Richard R. Heye , Robert D. Selinger , Menahem Lasser
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/1068 , G06F11/1072 , G06F2212/7201 , G11C16/04 , G11C16/0483
摘要： A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.
摘要翻译：公开了一种用于在主机设备和在闪存芯片上制造的闪存设备（例如，NAND闪存设备）之间进行接口的NAND控制器。在一些实施例中，本公开的NAND控制器包括制造在控制器管芯上的电子电路，控制器管芯与闪存管芯不同，第一接口（例如，主机型接口，例如，NAND接口），用于在电子电路和闪存设备，以及用于在控制器和主机设备之间进行接口的第二接口（例如，闪存型接口），其中第二接口是NAND接口。根据一些实施例，第一接口是管芯间接口。根据一些实施例，第一接口是NAND接口。还公开了包括当前公开的NAND控制器的系统。还公开了用于组装上述系统以及用于使用NAND控制器读取和写入数据的方法。

43. 发明授权

US08291295B2 NAND flash memory controller exporting a NAND interface 有权
标题翻译： NAND闪存控制器导出NAND接口
公开(公告)号：US08291295B2
公开(公告)日：2012-10-16
申请号：US12539417
申请日：2009-08-11
申请人： Eliyahou Harari , Richard R. Heye , Robert D. Selinger , Menahem Lasser
发明人： Eliyahou Harari , Richard R. Heye , Robert D. Selinger , Menahem Lasser
IPC分类号： G11C29/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F11/1072 , G06F2212/7201 , G11C16/04 , G11C16/0483
摘要： A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.
摘要翻译：公开了一种用于在主机设备和在闪存芯片上制造的闪存设备（例如，NAND闪存设备）之间进行接口的NAND控制器。在一些实施例中，本公开的NAND控制器包括制造在控制器管芯上的电子电路，控制器管芯与闪存管芯不同，第一接口（例如，主机型接口，例如，NAND接口），用于在电子电路和闪存设备，以及用于在控制器和主机设备之间进行接口的第二接口（例如，闪存型接口），其中第二接口是NAND接口。根据一些实施例，第一接口是管芯间接口。根据一些实施例，第一接口是NAND接口。还公开了包括当前公开的NAND控制器的系统。还公开了用于组装上述系统以及用于使用NAND控制器读取和写入数据的方法。

44. 发明授权

US08120068B2 Three-dimensional memory structures having shared pillar memory cells 有权
标题翻译：具有共享支柱存储单元的三维存储器结构
公开(公告)号：US08120068B2
公开(公告)日：2012-02-21
申请号：US12344022
申请日：2008-12-24
申请人： Roy E Scheuerlein , Eliyahou Harari
发明人： Roy E Scheuerlein , Eliyahou Harari
IPC分类号： H01L27/02
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/35 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.
摘要翻译：公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。共享支柱结构包括两个非易失性存储元件。每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。各个存储元件各自包括转向元件和状态改变元件。

45. 发明授权

US07994004B2 Flash memory cell arrays having dual control gates per memory cell charge storage element 有权
标题翻译：具有每个存储单元电荷存储元件的双控制栅极的闪存单元阵列
公开(公告)号：US07994004B2
公开(公告)日：2011-08-09
申请号：US12607444
申请日：2009-10-28
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42348 , H01L29/66825 , H01L29/7881
摘要： A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
摘要翻译：闪存NAND型EEPROM系统，其具有诸如浮置栅极的电荷存储元件阵列中的各个，与至少两个控制栅极线电容耦合。控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。结果，期望地增加存储单元耦合比。通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压，而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。控制栅极线也可以与衬底电容耦合，以选择性地提高其在所选浮栅的区域中的电压。通过形成间隔物的蚀刻掩模，可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。

46. 发明授权

US07951669B2 Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element 有权
标题翻译：制造具有每个存储单元电荷存储元件的双控制栅极的闪存单元阵列的方法
公开(公告)号：US07951669B2
公开(公告)日：2011-05-31
申请号：US11279725
申请日：2006-04-13
申请人： Eliyahou Harari , George Samachisa
发明人： Eliyahou Harari , George Samachisa
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/42336
摘要： Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline such the potential on individual floating gates are controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.
摘要翻译：描述了制造双重控制门非易失性存储器阵列的方法。平行的浮栅材料条在第一方向上形成在衬底上，但是由隧道电介质分离。在这些带之间的间隙中，控制栅极材料形成形成第二组平行条带，但与相邻浮栅条和基板两者绝缘。两组条带在垂直于第一方向的第二方向上被隔离，形成单独的浮动栅极和控制栅极的阵列。然后，由单独的控制栅极条形成的控制栅极通过导电字线互连，使得各个浮动栅极上的电位由两个相邻字线上的电压控制。在其他变型中，浮动栅极或控制栅极可以凹入原始衬底。

47. 发明授权

US07638834B2 Flash memory cell arrays having dual control gates per memory cell charge storage element 有权
标题翻译：具有每个存储单元电荷存储元件的双控制栅极的闪存单元阵列
公开(公告)号：US07638834B2
公开(公告)日：2009-12-29
申请号：US11422016
申请日：2006-06-02
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42348 , H01L29/66825 , H01L29/7881
摘要： A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
摘要翻译：闪存NAND型EEPROM系统，其具有诸如浮置栅极的电荷存储元件阵列中的各个，与至少两个控制栅极线电容耦合。控制栅极线优选地位于与浮动栅极的侧壁耦合的浮动栅极之间。结果，期望地增加存储单元耦合比。通常将所选行的浮置栅极的相对侧上的两个控制栅极线升高到相同的电压，而与所选行的紧邻和相对侧的未选择的浮动栅极行耦合的第二控制栅极线保持为低。控制栅极线也可以与衬底电容耦合，以选择性地提高其在所选浮栅的区域中的电压。通过形成间隔物的蚀刻掩模，可以使浮栅的长度和控制栅极线的厚度小于工艺的最小分辨率元件。

48. 发明授权

US07579247B2 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
标题翻译：采用介质存储元件的多状态非易失性集成电路存储器系统
公开(公告)号：US07579247B2
公开(公告)日：2009-08-25
申请号：US12020296
申请日：2008-01-25
申请人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
发明人： Eliyahou Harari , George Samachisa , Jack H. Yuan , Daniel C. Guterman
IPC分类号： H01L21/8239
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
摘要翻译：非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。每个单元中可以包括多于一个这样的共同区域。在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

49. 发明申请

US20090134228A1 MEMORY CARDS HAVING TWO STANDARD SETS OF CONTACTS AND A HINGED CONTACT COVERING MECHANISM 有权
标题翻译：具有两个标准联系人和铰链接触覆盖机构的记忆卡
公开(公告)号：US20090134228A1
公开(公告)日：2009-05-28
申请号：US12361165
申请日：2009-01-28
申请人： Robert C. Miller , Hem P. Takiar , Joel Jacobs , Robert Howard , Motohide Hatanaka , Robert F. Wallace , Edwin J. Cuellar , Eliyahou Harari
发明人： Robert C. Miller , Hem P. Takiar , Joel Jacobs , Robert Howard , Motohide Hatanaka , Robert F. Wallace , Edwin J. Cuellar , Eliyahou Harari
IPC分类号： G06K19/067 , G06F3/00
CPC分类号： G06K19/077 , G06K19/07732 , G06K19/07733 , G06K19/07741 , G06K19/07743 , H01R13/447 , H01R27/00
摘要： Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a memory card standard and that of the Universal Serial Bus (USB). One memory card standard that can be followed is that of the Secure Digital (SD) card. The cards can thus be used with different hosts that are compatible with one set of contacts but not the other. A cover that is hinged to the card to normally cover one set of contacts can be manually rotated out of the way when that set of contacts is being used.
摘要翻译：封闭的可重新编程的非易失性存储卡包括至少两组电触点，内部存储器与之连接。两组触点具有不同的图案，优选地根据两种不同的接触标准，例如存储卡标准和通用串行总线（USB）的标准。可以遵循的一种存储卡标准是安全数字（SD）卡的标准。因此，这些卡可以与与一组联系而不是另一组相容的不同主机使用。当使用该组触点时，铰接到卡上的盖通常覆盖一组触点可以手动旋转。

50. 发明授权

US07486555B2 Flash memory cell arrays having dual control gates per memory cell charge storage element 有权
公开(公告)号：US07486555B2
公开(公告)日：2009-02-03
申请号：US11379019
申请日：2006-04-17
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/42348 , H01L29/66825 , H01L29/7881
摘要： A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

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