专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20120320685A1 ERASE OPERATION CONTROL SEQUENCING APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：擦除操作控制测序装置，系统和方法
公开(公告)号：US20120320685A1
公开(公告)日：2012-12-20
申请号：US13599757
申请日：2012-08-30
申请人： Xiaojun Yu , Jin-man Han , Aaron Yip
发明人： Xiaojun Yu , Jin-man Han , Aaron Yip
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14
摘要： Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
摘要翻译：装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。

42. 发明申请

US20120218825A1 WORDLINE VOLTAGE TRANSFER APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译： WORDLINE电压转换装置，系统和方法
公开(公告)号：US20120218825A1
公开(公告)日：2012-08-30
申请号：US13465698
申请日：2012-05-07
申请人： Xiaojun Yu , Jin-man Han
发明人： Xiaojun Yu , Jin-man Han
IPC分类号： G11C16/10 , H01L21/8239
CPC分类号： G11C16/08
摘要： The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.
摘要翻译：本文描述的装置和系统可以包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管的调节器和字符串驱动器的字线驱动电路。调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。在一些实施例中，调节器可以包括共源共栅连接的晶体管对。还描述了制造和操作装置和系统的方法。

43. 发明授权

US08174900B2 Wordline voltage transfer apparatus, systems, and methods 有权
标题翻译：字线电压传输装置，系统和方法
公开(公告)号：US08174900B2
公开(公告)日：2012-05-08
申请号：US12698833
申请日：2010-02-02
申请人： Xiaojun Yu , Jin-man Han
发明人： Xiaojun Yu , Jin-man Han
IPC分类号： G11C16/06
CPC分类号： G11C16/08
摘要： The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.
摘要翻译：本文描述的装置和系统可以包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管的调节器和字符串驱动器的字线驱动电路。调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。在一些实施例中，调节器可以包括共源共栅连接的晶体管对。还描述了制造和操作装置和系统的方法。

44. 发明申请

US20110215321A1 POLYSILICON RESISTOR AND E-FUSE FOR INTEGRATION WITH METAL GATE AND HIGH-K DIELECTRIC 有权
标题翻译：用于与金属栅和高K电介质集成的多晶硅电阻器和电子熔断器
公开(公告)号：US20110215321A1
公开(公告)日：2011-09-08
申请号：US12719289
申请日：2010-03-08
申请人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
发明人： Roger A. Booth, JR. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
IPC分类号： H01L29/12 , H01L21/02 , H01L21/768 , H01L29/86 , H01L23/525
CPC分类号： H01L21/02 , H01L21/768 , H01L23/525 , H01L29/12 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.
摘要翻译：提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域，掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

45. 发明申请

US20110082680A1 COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS 失效
标题翻译：用于器件/电路/芯片泄漏电流（IDDQ）的紧凑型模型包括工艺引起的升级因素
公开(公告)号：US20110082680A1
公开(公告)日：2011-04-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50 , G06F17/18 , G01R31/26
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

46. 发明授权

US07825479B2 Electrical antifuse having a multi-thickness dielectric layer 有权
标题翻译：具有多层电介质层的电反熔丝
公开(公告)号：US07825479B2
公开(公告)日：2010-11-02
申请号：US12187003
申请日：2008-08-06
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei , Ravi M. Todi , Xiaojun Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/5252 , H01L27/11206 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.
摘要翻译：包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程电极，即晶体管的主体和栅电极，跨过栅极电介质。

47. 发明申请

US20100118611A1 DELAYED ACTIVATION OF SELECTED WORDLINES IN MEMORY 有权
标题翻译：延迟记忆中选定的文字的激活
公开(公告)号：US20100118611A1
公开(公告)日：2010-05-13
申请号：US12688600
申请日：2010-01-15
申请人： Xiaojun Yu , Jin-man Han
发明人： Xiaojun Yu , Jin-man Han
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C11/5642 , G11C8/14 , G11C16/08 , G11C16/32
摘要： Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.
摘要翻译：装置，系统和方法可以操作以在耦合到存储器阵列的控制电路处接收外部读取命令。可以根据由包括在阵列中的多个存储器单元相关联的读取电平电压幅度确定的延迟周期来延迟单独的字线激活。

48. 发明申请

US20080186775A1 Wordline voltage transfer apparatus, systems, and methods 有权
标题翻译：字线电压传输装置，系统和方法
公开(公告)号：US20080186775A1
公开(公告)日：2008-08-07
申请号：US11702261
申请日：2007-02-05
申请人： Xiaojun Yu , Jin-man Han
发明人： Xiaojun Yu , Jin-man Han
IPC分类号： G11C16/08
CPC分类号： G11C16/08
摘要： The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.
摘要翻译：本文描述的装置和系统可以包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管的调节器和字符串驱动器的字线驱动电路。调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。在一些实施例中，调节器可以包括共源共栅连接的晶体管对。还描述了制造和操作装置和系统的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式