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    • 41. 发明授权
    • Apparatus for forming thin film
    • 用于形成薄膜的装置
    • US08999064B2
    • 2015-04-07
    • US13179463
    • 2011-07-08
    • Sang-Woo Lee
    • Sang-Woo Lee
    • C23C16/00C23C14/24C23C14/12
    • C23C14/243C23C14/12
    • A thin film forming apparatus according to the embodiment includes a plurality of vapor deposition sources respectively separated from each other, a plurality of nozzle bodies connected to upper portions of the respective vapor deposition sources, and a plurality of nozzles connected to upper portions of the respective nozzle bodies. A nozzle hole of each of the nozzles is formed on a same vapor deposition line. Thus, according to the embodiment, the first organic material and the second organic material respectively sprayed through a first nozzle hole and a second nozzle hole can be uniformly mixed by disposing the first nozzle hole and the second nozzle on the same vapor deposition line.
    • 根据实施例的薄膜形成装置包括分别彼此分离的多个气相沉积源,连接到各个蒸镀源的上部的多个喷嘴体,以及连接到各个蒸镀源的上部的多个喷嘴 喷嘴体。 每个喷嘴的喷嘴孔形成在相同的蒸镀线上。 因此,根据本实施例,通过将第一喷嘴孔和第二喷嘴设置在相同的蒸镀线上,能够均匀地混合通过第一喷嘴孔和第二喷嘴孔喷射的第一有机材料和第二有机材料。
    • 50. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US08030204B2
    • 2011-10-04
    • US12217932
    • 2008-07-10
    • Jin-Ho ParkGil-Heyun ChoiSang-Woo LeeHo-Ki Lee
    • Jin-Ho ParkGil-Heyun ChoiSang-Woo LeeHo-Ki Lee
    • H01L21/4763
    • H01L23/485H01L21/28562H01L21/76846H01L21/76865H01L27/10891H01L2924/0002H01L2924/00
    • In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
    • 在形成半导体器件的布线结构的方法中,在其上定位有多个导电结构的半导体衬底上形成绝缘层。 绝缘层的上表面被平坦化,并且导电结构之间的空间被绝缘层填充。 绝缘层从衬底部分地移除以形成至少一个开口,衬底通过该开口被部分暴露。 在所述至少一个开口的侧壁的底部和下部形成残余金属层,并且在所述残余金属层和所述开口的上侧壁上用金属材料形成金属氮化物层。 因此,可以防止在用于形成金属插塞的平坦化处理中去除阻挡层的上部。