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41. 发明授权

US5448181A Output buffer circuit having reduced switching noise 失效
标题翻译：输出缓冲电路具有降低的开关噪声
公开(公告)号：US5448181A
公开(公告)日：1995-09-05
申请号：US310203
申请日：1994-09-20
申请人： David Chiang
发明人： David Chiang
IPC分类号： H03K19/003 , H03K19/094 , H03K17/16 , H03K19/0948
CPC分类号： H03K19/09429 , H03K19/00361
摘要： A CMOS or NMOS output buffer equalizes the number of logic gates in the signal paths connected to both the pull up and pull down transistors. In one embodiment, the pull down transistor signal path includes the conventional inverter connected to the output of a NAND gate. The pull up transistor signal path includes a CMOS passgate including two transistors connected together controlled by the output enable signal and passing the output data signal to a conventional output inverter stage. Also an additional transistor controlled by the output enable signal provides an additional signal to the input of the pull up transistor output inverter stage when the output enable signal is low. The provision of balanced signal paths in terms of number of gates and therefore propagation time to both the pull up and pull down transistors evens out the rise and fall crowbar switching current and thus minimizes switching noise.
摘要翻译： CMOS或NMOS输出缓冲器均衡连接到上拉和下拉晶体管的信号路径中的逻辑门数。在一个实施例中，下拉晶体管信号路径包括连接到NAND门的输出的常规反相器。上拉晶体管信号路径包括CMOS通道，其包括由输出使能信号连接在一起的两个晶体管，并将输出数据信号传递到常规的输出反相器级。另外，当输出使能信号为低电平时，由输出使能信号控制的附加晶体管也向上拉晶体管输出反相器级的输入端提供附加信号。根据门数量提供平衡信号路径，从而提供上拉和下拉晶体管的传播时间，可以提高和降低撬棒开关电流，从而最大限度地减少开关噪声。

42. 发明授权

US5349249A Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading 失效
标题翻译：可编程逻辑器件具有位于配置位位置之间的安全元件，以防止未经授权的读取
公开(公告)号：US5349249A
公开(公告)日：1994-09-20
申请号：US43882
申请日：1993-04-07
申请人： David Chiang , Thomas Y. Ho , Wei-Yi Ku , George H. Simmons , Robert W. Barker
发明人： David Chiang , Thomas Y. Ho , Wei-Yi Ku , George H. Simmons , Robert W. Barker
IPC分类号： G06F12/14 , G06F21/79 , H03K19/177 , H04L9/10 , H04L9/00
CPC分类号： H01L23/57 , G06F12/1425 , G06F21/79 , H01L2924/0002
摘要： More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to the areas containing configuration and any other user-defined data, both so that they are difficult to discover and so that the erasure of all security bits in a EPROM-based PLD would cause a large number of adjacent user-defined bits to be erased as well, hence making it very difficult to extract useful information from a protected device by reverse engineering. Situating security bits in a different, pseudorandom location within each block of the chip makes them difficult to find and so further inhibits reverse engineering.
摘要翻译：在PLD芯片的一个块中使用了多个安全位。当所有安全位都处于擦除状态时，内部配置和其他信息将不受保护，并通过编程一个或所有安全位进行保护。安全位在物理上位于包含配置和任何其他用户定义的数据的区域附近，这两者都难以发现，并且使得基于EPROM的PLD中所有安全位的擦除将导致大量相邻的用户定义的位也被擦除，因此通过逆向工程从受保护的设备中提取有用的信息非常困难。在芯片的每个块内的不同的伪随机位置将安全位置于状态，使得它们难以找到，因此进一步禁止逆向工程。

43. 发明授权

US5185805A Tuned deconvolution digital filter for elimination of loudspeaker output blurring 失效
标题翻译：调谐去卷积数字滤波器，用于消除扬声器输出模糊
公开(公告)号：US5185805A
公开(公告)日：1993-02-09
申请号：US628635
申请日：1990-12-17
申请人： David Chiang
发明人： David Chiang
IPC分类号： H04R3/04
CPC分类号： H04R3/04
摘要： A FIR (finite impulse response) type digital filter operates on digital audio signals in modern sound reproduction systems. It is shown that this operation forces the loudspeaker to produce a sound pressure wave having the original signal waveform. Given a multi-driver speaker, its response to a known broad band analog signal (impulsive) is sampled at least as fast as the Nyquist rate. The result is used to construct a deconvolution filter which compacts, in the least-squares sense, the blurred signal (speaker output) back into its original waveform. Since this anti-blurring process is linear and time invariant, it can be applied to the speaker driving signal as a blur preventive. A fine-tuning procedure utilizing Lagrange's Method of Multipliers modifies the deconvolution process such that the blur-free speaker output achieves a degree of flatness in frequency response beyond what could be attained with a simple deconvolution filter.
摘要翻译： FIR（有限脉冲响应）型数字滤波器对现代声音再现系统中的数字音频信号进行操作。这表明该操作迫使扬声器产生具有原始信号波形的声压波。给定多驱动器扬声器，其对已知宽带模拟信号（脉冲）的响应至少与奈奎斯特速率一样快。结果用于构造一个去卷积滤波器，它将最小二乘意义上的模糊信号（扬声器输出）压缩回其原始波形。由于这种抗模糊处理是线性和时间不变的，所以它可以作为模糊预防应用于扬声器驱动信号。使用拉格朗日乘数法的微调程序修改了去卷积处理，使得无模糊的扬声器输出达到了超过使用简单去卷积滤波器可达到的频率响应的平坦度。

44. 发明授权

US08259666B2 Femto-BTS RF access mechanism 有权
标题翻译：毫微微BTS射频接入机制
公开(公告)号：US08259666B2
公开(公告)日：2012-09-04
申请号：US13345465
申请日：2012-01-06
申请人： Derek Hongwei Bao , David Chiang
发明人： Derek Hongwei Bao , David Chiang
IPC分类号： H04W4/00
CPC分类号： H04W48/12 , H04W48/16 , H04W84/045
摘要： Femto cells that extend mobile network coverage into customer premises operate in a frequency band typically assigned to a macro network. To facilitate system discovery and registrations of mobile stations with femto cells, a carrier designates one the channels within the band as a primary channel for its femto cells. For example, neighbor list messages transmitted by macro network base stations can provide frequency and PN code information directing mobile stations to search the primary channel for a PN code of the femto cells. The mobile station preferred roaming list (PRL) may identify femto cells by SID/NID. The SID is that of the carrier's macro network, whereas the NID may be a NID of the macro network or one specifically assigned to femto cell operations. The PRL uses frequency acquisition information for the femto cells that is the same as or similar to that for one of the macro networks.
摘要翻译：将移动网络覆盖扩展到客户驻地的毫微微小区在通常分配给宏网络的频带中操作。为了促进具有毫微微小区的移动站的系统发现和注册，载波将频带内的信道指定为其毫微微小区的主要信道。例如，由宏网络基站发送的邻居列表消息可以提供频率和PN码信息，其指示移动台在主信道上搜索毫微微小区的PN码。移动台优选漫游列表（PRL）可以通过SID / NID来识别毫微微小区。 SID是运营商的宏网络的SID，而NID可以是宏网络的NID或专门分配给毫微微小区操作的NID。 PRL使用与一个宏网络相同或类似的毫微微小区的频率获取信息。

45. 发明申请

US20080084557A1 Optical inspection system 审中-公开
标题翻译：光学检测系统
公开(公告)号：US20080084557A1
公开(公告)日：2008-04-10
申请号：US11599968
申请日：2006-11-15
申请人： Wei Song Tan , David Chiang , Todd Aldridge Russell
发明人： Wei Song Tan , David Chiang , Todd Aldridge Russell
IPC分类号： G01N21/958 , G01N21/95
CPC分类号： G01N21/8806 , G01N21/958 , G01N2021/9511
摘要： The present invention relates to an optical system that allows accurate projection and inspection of a curved surface onto a flat plane. The present invention may be used to prevent or mitigate inspection errors caused by particulate matter by narrowing the depth of field along a curved surface.
摘要翻译：光学系统技术领域本发明涉及一种允许将曲面精确地投影到平面上的光学系统。本发明可以用于通过沿着曲面缩小景深来防止或减轻由颗粒物质引起的检查误差。

46. 发明授权

US5450021A EPLD chip with hybrid architecture optimized for both speed and flexibility 失效
标题翻译：具有针对速度和灵活性优化的混合架构的EPLD芯片
公开(公告)号：US5450021A
公开(公告)日：1995-09-12
申请号：US234097
申请日：1994-04-28
申请人： David Chiang
发明人： David Chiang
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094 , H03K19/177
CPC分类号： H03K19/17792 , H03K19/018507 , H03K19/09429 , H03K19/17704
摘要： A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.
摘要翻译：混合EPLD（芯片）架构具有多个第一块，每个第一块包括第一类型可编程AND阵列和多个第一类型的宏单元，其结构复杂且高度可配置; 以及多个块，每个包括具有比第一类型AND阵列少的输入线和产品项输出线的第二类型可编程AND阵列，以及具有比第一类宏单元更少的逻辑门的多个第二类型宏单元。 EPLD具有用于互连所有块的可编程互连矩阵。

47. 发明授权

US5384499A High-density erasable programmable logic device architecture using multiplexer interconnections 失效
标题翻译：使用多路复用器互连的高密度可擦除可编程逻辑器件架构
公开(公告)号：US5384499A
公开(公告)日：1995-01-24
申请号：US123435
申请日：1993-09-17
申请人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
发明人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
摘要翻译：提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。

48. 发明授权

US5362999A EPLD chip with hybrid architecture optimized for both speed and flexibility 失效
标题翻译：具有针对速度和灵活性优化的混合架构的EPLD芯片
公开(公告)号：US5362999A
公开(公告)日：1994-11-08
申请号：US32920
申请日：1993-03-18
申请人： David Chiang
发明人： David Chiang
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094 , H03K19/177
CPC分类号： H03K19/17792 , H03K19/018507 , H03K19/09429 , H03K19/17704
摘要： A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.
摘要翻译：混合EPLD（芯片）架构具有多个第一块，每个第一块包括第一类型可编程AND阵列和多个第一类型的宏单元，其结构复杂且高度可配置; 以及多个块，每个包括具有比第一类型AND阵列少的输入线和产品项输出线的第二类型可编程AND阵列，以及具有比第一类宏单元更少的逻辑门的多个第二类型宏单元。 EPLD具有用于互连所有块的可编程互连矩阵。

49. 发明授权

US5329174A Circuit for forcing known voltage on unconnected pads of an integrated circuit 失效
标题翻译：用于在集成电路的未连接焊盘上强制已知电压的电路
公开(公告)号：US5329174A
公开(公告)日：1994-07-12
申请号：US965636
申请日：1992-10-23
申请人： David Chiang
发明人： David Chiang
IPC分类号： H03K3/356 , H03K17/22 , H03K17/16 , H03K3/26
CPC分类号： H03K3/356008 , H03K17/223
摘要： A feedback circuit for input pads of an integrated circuit where one or more of the input pads may not be bonded to a package pin when the pad is packaged or alternatively is bonded but the pin is not externally connected. The feedback circuit includes a transistor connected between the input pad and the output of the first associated input buffer so that whenever the integrated circuit is at a steady state, i.e. is off or has been powered on, no direct current is drawn by the pad because the unbonded pad is forced to be either in the high or low state by the feedback transistor. The feedback transistor may be a pull down device or a pull up device or a full inverting gate; in any case the feedback device draws no direct current when the input pad connected thereto is at its fully high or fully low state voltage.
摘要翻译：一种用于集成电路的输入焊盘的反馈电路，其中一个或多个输入焊盘在焊盘封装或替代地接合但引脚不外部连接时，可能不会与封装引脚接合。反馈电路包括连接在输入焊盘和第一相关联的输入缓冲器的输出之间的晶体管，使得每当集成电路处于稳定状态（即关断或已通电时），由于焊盘不会直接吸引电流，因为未结合的焊盘被反馈晶体管强制为处于高或低状态。反馈晶体管可以是下拉器件或上拉器件或全反相栅极; 在任何情况下，当与其连接的输入焊盘处于其完全高或完全低电压状态时，反馈装置不吸收直流电流。

50. 发明授权

US4438379A Method of damping a stepping motor 失效
标题翻译：阻尼步进电机的方法
公开(公告)号：US4438379A
公开(公告)日：1984-03-20
申请号：US273625
申请日：1981-06-15
申请人： David Chiang , Mosi Chu , Solomon Manber
发明人： David Chiang , Mosi Chu , Solomon Manber
IPC分类号： H02P8/32 , G05B19/40
CPC分类号： H02P8/32
摘要： For a stepping motor having a rotatable stator magnetic field for driving the rotor, there is disclosed a method of damping the oscillations of the rotor which occurs when the rotatable stator magnetic field is stopped upon arriving at a desired rotational position by measuring quantities related to the instantaneous velocity of the rotor due to the oscillations of the rotor about the desired rotational position, rotationally displacing the stator magnetic field from the desired rotational position in a direction opposite to the direction of the oscillation, and thereafter returning the stator magnetic field to the desired stopping position.
摘要翻译：对于具有用于驱动转子的可旋转定子磁场的步进电动机，公开了一种阻尼转子振荡的方法，该方法是当可旋转的定子磁场在到达期望的旋转位置时停止，通过测量与由于转子围绕期望的旋转位置的振荡而导致的转子的瞬时速度，在与振荡方向相反的方向上将定子磁场从期望的旋转位置旋转移位，然后将定子磁场返回到期望的停止位置

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