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41. 发明授权

US07498622B1 Latchup robust gate array using through wafer via 有权
标题翻译：使用通过晶片通孔的Latchup鲁棒门阵列
公开(公告)号：US07498622B1
公开(公告)日：2009-03-03
申请号：US11956417
申请日：2007-12-14
申请人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L31/112
CPC分类号： H01L27/11807 , H01L21/743 , H01L27/0921
摘要： A structure and a method for preventing latchup in a gate array. The structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.
摘要翻译：一种防止门阵列闭锁的结构和方法。该结构包括：衬底中的NFET栅极阵列和PFET门阵列; 从衬底的底表面朝向衬底的顶表面延伸的导电通孔，NFET栅极阵列和PFET门阵列，通孔电接触P阱。

42. 发明申请

US20080265333A1 STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS 审中-公开
标题翻译：结构和方法，增强三重保护锁定稳定性
公开(公告)号：US20080265333A1
公开(公告)日：2008-10-30
申请号：US12169667
申请日：2008-07-09
申请人： David S. Collins , James A. Slinkman , Steven H. Voldman
发明人： David S. Collins , James A. Slinkman , Steven H. Voldman
IPC分类号： H01L27/06
CPC分类号： H01L27/0928 , H01L21/761 , H01L27/0921 , H01L29/1087
摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.
摘要翻译：公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p衬底隔离以及在n阱下方。该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

43. 发明申请

US20080134104A1 DESIGN METHODOLOGY OF GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION 失效
标题翻译：防护套设计电阻优化的设计方法LATCHUP PREVENTION
公开(公告)号：US20080134104A1
公开(公告)日：2008-06-05
申请号：US11566922
申请日：2006-12-05
申请人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS circuit and the corresponding power supply. By comparing the calculated guard ring to power supply path resistance value to resistance criteria derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit.
摘要翻译：公开了一种通过优化保护环到CMOS电路中的物理和/或虚拟注入源之间的供电路径电阻值和相应的电源来优化保护环设计的设计方法。通过将计算出的保护环与电源路径电阻值进行比较，可以确定需要进一步重新设计的元件。通过多次重新设计的重新设计，最终会导致优化的保护环结构，为CMOS电路提供区域高效和足够的锁存保护。

44. 发明授权

US08420518B2 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry 有权
标题翻译：在CMOS电路中通过晶片通孔放置的闭锁稳健性的结构和方法
公开(公告)号：US08420518B2
公开(公告)日：2013-04-16
申请号：US13095158
申请日：2011-04-27
申请人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L21/22
CPC分类号： H01L27/0921 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L23/481 , H01L27/092 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
摘要翻译：一种制造半导体结构的方法包括：在衬底的背面形成沟槽; 在沟槽的表面上沉积掺杂剂; 在与沟槽相对的衬底的顶侧中形成浅沟槽隔离（STI）结构; 在基材中形成深井; 将掺杂剂扩散到深阱和衬底中; 在衬底中形成N阱和P阱; 以及用导电材料填充沟槽。

45. 发明申请

US20110147808A1 ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：非对称结场效应晶体管
公开(公告)号：US20110147808A1
公开(公告)日：2011-06-23
申请号：US13037485
申请日：2011-03-01
申请人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
IPC分类号： H01L27/098
CPC分类号： H01L29/1058 , H01L29/0653 , H01L29/0692 , H01L29/0843 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
摘要翻译：半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。下栅极区域电连接到上栅极区域。上下栅极区域控制通过沟道区域的电流。通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

46. 发明申请

US20110018060A1 METHOD AND STRUCTURES FOR IMPROVING SUBSTRATE LOSS AND LINEARITY IN SOI SUBSTRATES 有权
标题翻译：改善SOI衬底中衬底损耗和线性的方法和结构
公开(公告)号：US20110018060A1
公开(公告)日：2011-01-27
申请号：US12507150
申请日：2009-07-22
申请人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
发明人： Alan Bernard Botula , David S. Collins , Alvin Jose Joseph , Howard Smith Landis , James Albert Slinkman , Anthony K. Stamper
IPC分类号： H01L27/12 , H01L21/762 , H01L29/06
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/3226 , H01L21/76283 , H01L27/1203
摘要： Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.
摘要翻译：改善SOI衬底的衬底损耗和线性度的方法和结构。这些方法包括在SOI衬底的掩埋氧化物层下面形成损坏的晶体结构区域，并且其结构包括在SOI衬底的掩埋氧化物层下面的损坏的晶体结构区域。

47. 发明授权

US07855420B2 Structure for a latchup robust array I/O using through wafer via 有权
标题翻译：用于通过晶片通孔的闭锁鲁棒阵列I / O的结构
公开(公告)号：US07855420B2
公开(公告)日：2010-12-21
申请号：US12043163
申请日：2008-03-06
申请人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： H01L21/76229 , H01L21/76264 , H01L21/823878 , H01L23/481 , H01L27/0251 , H01L27/0921 , H01L2924/0002 , H01L2924/00
摘要： A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.
摘要翻译：一种设计结构，包括：在包含逻辑电路的集成电路芯片的区域中的I / O单元和ESD保护电路; 导电通孔，其从所述基板的底表面延伸到所述I / O单元和ESD保护电路之间的所述基板的顶表面以及所述逻辑电路中的至少一个。

48. 发明申请

US20100264545A1 Metal Fill Structures for Reducing Parasitic Capacitance 有权
标题翻译：用于减少寄生电容的金属填充结构
公开(公告)号：US20100264545A1
公开(公告)日：2010-10-21
申请号：US12632838
申请日：2009-12-08
申请人： David S. Collins , Howard S. Landis , Anthony K. Stamper , Janet M. Wilson
发明人： David S. Collins , Howard S. Landis , Anthony K. Stamper , Janet M. Wilson
IPC分类号： H01L23/522
CPC分类号： H01L23/522 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Vertically-staggered-level metal fill structures include inner contiguous metal fill structures and outer contiguous metal fill structures. A dielectric material portion is provided between each contiguous metal fill structure. Vertical extent of each contiguous metal fill structure is limited up to three vertically adjoining metal interconnect levels, thereby limiting the capacitance of each contiguous metal fill structure. Capacitive coupling between the contiguous metal fill structures and the metal interconnect structures is minimized due to the fragmented structure of contiguous metal fill structures.
摘要翻译：垂直交错的金属填充结构包括内部相邻的金属填充结构和外部连续的金属填充结构。在每个邻接的金属填充结构之间提供电介质材料部分。每个连续金属填充结构的垂直范围被限制到三个垂直相邻的金属互连水平，从而限制每个相邻的金属填充结构的电容。由于连续的金属填充结构的分段结构，连续的金属填充结构和金属互连结构之间的电容耦合被最小化。

49. 发明申请

US20100207173A1 ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：非对称结场效应晶体管
公开(公告)号：US20100207173A1
公开(公告)日：2010-08-19
申请号：US12388586
申请日：2009-02-19
申请人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
IPC分类号： H01L29/772 , H01L21/337 , H01L21/762
CPC分类号： H01L29/1058 , H01L29/0653 , H01L29/0692 , H01L29/0843 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
摘要翻译：半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。下栅极区域电连接到上栅极区域。上下栅极区域控制通过沟道区域的电流。通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。

50. 发明授权

US07741681B2 Latchup robust array I/O using through wafer via 失效
标题翻译：使用通过晶片通孔的Latchup鲁棒阵列I / O
公开(公告)号：US07741681B2
公开(公告)日：2010-06-22
申请号：US11956386
申请日：2007-12-14
申请人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip Francis Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： H01L27/0921 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.
摘要翻译：一种用于防止闩锁的结构和方法。该结构包括：在包含逻辑电路的集成电路芯片的区域中的I / O单元和ESD保护电路; 导电通孔，其从所述基板的底表面延伸到所述I / O单元和ESD保护电路之间的所述基板的顶表面以及所述逻辑电路中的至少一个。

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