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41. 发明申请

US20070255935A1 Tracing through reset 有权
公开(公告)号：US20070255935A1
公开(公告)日：2007-11-01
申请号：US11820546
申请日：2007-06-20
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F15/177
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

42. 发明授权

US07254704B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07254704B2
公开(公告)日：2007-08-07
申请号：US11359158
申请日：2006-02-21
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

43. 发明申请

US20070094644A1 Programmable Extended Compression Mask for Dynamic Trace 有权
标题翻译：用于动态跟踪的可编程扩展压缩掩码
公开(公告)号：US20070094644A1
公开(公告)日：2007-04-26
申请号：US11566762
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John Johnsen
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的比较地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与比较地址不匹配或者比当前跟踪地址与比较地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。比较地址由中央处理单元通过存储器映射寄存器写入操作指定。

44. 发明申请

US20070094546A1 Progressive Extended Compression Mask for Dynamic Trace 有权
公开(公告)号：US20070094546A1
公开(公告)日：2007-04-26
申请号：US11566757
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John Johnsen
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.

45. 发明授权

US07171497B2 Progressive extended compression mask for dynamic trace 有权
标题翻译：逐行扩展压缩掩码，用于动态跟踪
公开(公告)号：US07171497B2
公开(公告)日：2007-01-30
申请号：US10301969
申请日：2002-11-22
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

46. 发明授权

US07162552B2 Programmable extended compression mask for dynamic trace 有权
标题翻译：可编程扩展压缩掩模，用于动态跟踪
公开(公告)号：US07162552B2
公开(公告)日：2007-01-09
申请号：US10302189
申请日：2002-11-22
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的比较地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与比较地址不匹配或者比当前跟踪地址与比较地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。比较地址由中央处理单元通过存储器映射寄存器写入操作指定。

47. 发明授权

US07127387B2 Multi-port trace data handling 有权
标题翻译：多端口跟踪数据处理
公开(公告)号：US07127387B2
公开(公告)日：2006-10-24
申请号：US10302193
申请日：2002-11-22
申请人： Manisha Agarwala , Lewis Nardini , John M. Johnsen , Maria B. H. Gill , Jose L. Flores
发明人： Manisha Agarwala , Lewis Nardini , John M. Johnsen , Maria B. H. Gill , Jose L. Flores
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译：跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送港口。如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。

48. 发明申请

US20060200805A1 Reporting a Saturated Counter Value 有权
标题翻译：报告饱和计数器值
公开(公告)号：US20060200805A1
公开(公告)日：2006-09-07
申请号：US11383335
申请日：2006-05-15
申请人： Manisha Agarwala , John Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John Johnsen , Lewis Nardini
IPC分类号： G06F9/44
CPC分类号： G06F11/261
摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
摘要翻译：饱和计数将接收的事件信号计数到第一预定数量。溢出计数器计数溢出到第二预定数量。当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。可以通过寄存器读取操作读取计数器。第一预定位数和第二预定位数之和为8位的整数倍的总和。

49. 发明申请

US20050188182A1 Microprocessor having a set of byte intermingling instructions 审中-公开
标题翻译：微处理器具有一组字节混合指令
公开(公告)号：US20050188182A1
公开(公告)日：2005-08-25
申请号：US11114549
申请日：2005-04-26
申请人： David Hoyle , Vishal Markandey , Lewis Nardini
发明人： David Hoyle , Vishal Markandey , Lewis Nardini
IPC分类号： G06F15/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/3828 , G06F9/3853 , G06F9/3891
摘要： A data processing system is provided with a digital signal processor that has a set of instructions for intermingling byte fields selected from a selected pair of source operands and storing the ordered result in a selected destination register. A first 32-bit operand is treated as four 8-bit fields while a second 32-bit operand is treated as four 8-bit fields. Intermingling circuitry is operable to form an ordered result in accordance with each one of the set of byte intermingling instructions. An instruction is provided that performs a shift right and byte merge operation. Another instruction is provided that performs a shift left and byte merge operation. Another instruction is provided that perform a byte swap operation. A set of instructions are provided that perform various byte packing and unpacking operations.
摘要翻译：数据处理系统具有数字信号处理器，该数字信号处理器具有一组指令，用于混合从所选择的一对源操作数中选择的字节字段，并将所选择的结果存储在所选择的目标寄存器中。第一个32位操作数被视为四个8位字段，而第二个32位操作数被视为四个8位字段。混合电路可操作以根据该组字节混合指令中的每一个形成有序结果。提供执行右移和字节合并操作的指令。另外提供了执行左移和字节合并操作的指令。提供另一个执行字节交换操作的指令。提供了一组执行各种字节打包和解包操作的指令。

50. 发明授权

US06745319B1 Microprocessor with instructions for shuffling and dealing data 有权
标题翻译：具有混洗和交易数据指令的微处理器
公开(公告)号：US06745319B1
公开(公告)日：2004-06-01
申请号：US09702452
申请日：2000-10-31
申请人： Keith Balmer , David Hoyle , Lewis Nardini
发明人： Keith Balmer , David Hoyle , Lewis Nardini
IPC分类号： G06F9305
CPC分类号： G06F9/3891 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3828 , G06F9/3885
摘要： A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.
摘要翻译：数据处理系统具有数字信号处理器（DSP），数字信号处理器（DSP）具有用于混洗源操作数（600）并将洗牌结果存储在所选目的地寄存器（610）中的混洗指令。通过从来自第二操作数部分的位与第一源操作数部分交织比特来形成混洗结果。提供去交错和包（DEAL）指令用于解交织源操作数。随机播放指令和DEAL指令具有完全相反的效果。 DSP包括在单个执行阶段执行交织或解交织的交换电路。

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