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41. 发明申请

US20050095854A1 Methods for depositing high yield and low defect density conductive films in damascene structures 审中-公开
标题翻译：在镶嵌结构中沉积高产率和低缺陷密度导电膜的方法
公开(公告)号：US20050095854A1
公开(公告)日：2005-05-05
申请号：US10698878
申请日：2003-10-31
申请人： Cyprian Uzoh , Bulent Basol
发明人： Cyprian Uzoh , Bulent Basol
IPC分类号： H01L21/288 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/2885
摘要： A process of electrodepositing a substantially flat conductive layer on a workpiece surface is provided. In the process, various transition current densities are determined experimentally by evaluating the effects of the plating current density on gap fill profile in the smallest cavities with the largest tendency to over-plate on the substrate. After determining the transition currents on experimental wafers or dies, an electrochemical plating process is performed to apply selected transition current densities as process current densities to form a substantially flat profile over the smallest cavities.
摘要翻译：提供了在工件表面上电沉积基本平坦的导电层的工艺。在此过程中，通过评估电镀电流密度对最小空腔中的间隙填充轮廓的影响，在基板上具有最大的过平板倾向，实验确定了各种转变电流密度。在确定实验晶片或裸片上的转换电流之后，执行电化学电镀工艺以将所选择的过渡电流密度用作过程电流密度，以在最小空腔上形成基本平坦的轮廓。

42. 发明申请

US20070135022A1 Apparatus for reduction of defects in wet procssed layers 有权
标题翻译：用于减少湿底层缺陷的设备
公开(公告)号：US20070135022A1
公开(公告)日：2007-06-14
申请号：US11704631
申请日：2007-02-09
申请人： Bulent Basol , Cyprian Uzoh
发明人： Bulent Basol , Cyprian Uzoh
IPC分类号： B24B49/00
CPC分类号： B24B57/02 , B24B37/042 , C23C18/1617 , C23C18/38 , C25D7/123 , C25D21/04 , C25D21/18 , H01L21/2885
摘要： The present invention provides an apparatus for wet processing of a conductive layer using a degassed process solution such as a degassed electrochemical deposition solution, a degassed electrochemical polishing solution, a degassed deposition solution, and a degassed cleaning solution. The technique includes degassing the process solution before delivering the degassed process solution to a processing unit or degassing the process solution in situ, within the processing unit.
摘要翻译：本发明提供一种使用脱气的电解沉积溶液，脱气电化学抛光溶液，脱气沉积溶液和脱气清洗溶液等脱气工艺溶液对导电层进行湿法加工的设备。该技术包括在将脱气的处理溶液递送到处理单元之前对处理溶液进行脱气或在处理单元内原位脱气处理溶液。

43. 发明申请

US20060009033A1 Defect-free thin and planar film processing 审中-公开
标题翻译：无缺陷的薄和平面薄膜加工
公开(公告)号：US20060009033A1
公开(公告)日：2006-01-12
申请号：US11226511
申请日：2005-09-13
申请人： Bulent Basol , Cyprian Uzoh
发明人： Bulent Basol , Cyprian Uzoh
IPC分类号： H01L21/461 , C25D17/00
CPC分类号： C25D17/001 , C25D7/123 , H01L21/2885 , H01L21/32125 , H01L21/7684 , H01L21/76877
摘要： The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.
摘要翻译：本发明的方法在半导体晶片表面中形成铜互连。在该过程中，最初，在晶片的顶表面中提供窄且大的特征，然后通过使用电化学沉积工艺沉积初级铜层。初级铜层完全填满了特征，并在狭窄的特征上形成一个平坦的表面，在大的特征上形成一个非平面的表面。通过采用电化学机械沉积工艺，将二次铜层沉积在初级铜层上，以形成窄和大特征上的平面铜层。在该工艺步骤之后，使用电解抛光工艺来减小平面铜层的厚度。

44. 发明申请

US20050006244A1 Electrode assembly for electrochemical processing of workpiece 有权
标题翻译：工件电化学处理用电极组件
公开(公告)号：US20050006244A1
公开(公告)日：2005-01-13
申请号：US10723045
申请日：2003-11-26
申请人： Cyprian Uzoh , Bulent Basol
发明人： Cyprian Uzoh , Bulent Basol
IPC分类号： C25D5/08 , C25D7/12 , C25D17/14 , C25F7/00 , H01L21/288 , H01L21/321 , H01L21/3213 , H01L21/768 , C25D5/20 , C25D21/10
CPC分类号： H01L21/2885 , C25D5/08 , C25D7/12 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/32115 , H01L21/3212 , H01L21/32134 , H01L21/76877
摘要： The present invention provides a novel system, apparatus, and method to deposit conductive films on a workpiece. A system for electroplating a surface of a workpiece using a process solution is disclosed. The system comprises a solution housing configured to house an electrode and to contain the process solution, a filter element disposed in the solution housing configured to partition the solution housing into a lower chamber and an upper chamber, and an upper inlet port coupled to the solution housing configured to deliver the process solution to the upper chamber of the solution housing to fill the upper chamber and the lower chamber immersing the electrode in the lower chamber.
摘要翻译：本发明提供了一种在工件上沉积导电膜的新型系统，装置和方法。公开了一种使用工艺溶液对工件的表面进行电镀的系统。该系统包括配置成容纳电极并容纳处理溶液的溶液壳体，设置在溶液壳体中的过滤元件，构造成将溶液壳体分隔成下腔室和上腔室，以及连接到溶液的上入口端口壳体，被配置为将处理溶液输送到溶液壳体的上腔室以填充上室，下室将电极浸入下室中。

45. 发明授权

US08609540B2 Reliable packaging and interconnect structures 有权
标题翻译：可靠的包装和互连结构
公开(公告)号：US08609540B2
公开(公告)日：2013-12-17
申请号：US13164448
申请日：2011-06-20
申请人： Cyprian Uzoh , Belgacem Haba , Craig Mitchell
发明人： Cyprian Uzoh , Belgacem Haba , Craig Mitchell
IPC分类号： H01L21/32
CPC分类号： H01L23/528 , H01L21/2885 , H01L21/3212 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76868 , H01L21/76873 , H01L21/76879 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/53209 , H01L23/53238 , H01L24/13 , H01L24/14 , H01L2221/1094 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/13025 , H01L2224/13111 , H01L2224/14181 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
摘要翻译：提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。在一些实施例中，异种材料可以是导电材料或纳米合金。互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

46. 发明授权

US06582579B1 Methods for repairing defects on a semiconductor substrate 有权
标题翻译：用于修复半导体衬底上的缺陷的方法
公开(公告)号：US06582579B1
公开(公告)日：2003-06-24
申请号：US09534704
申请日：2000-03-24
申请人： Cyprian Uzoh
发明人： Cyprian Uzoh
IPC分类号： C25D502
CPC分类号： H01L21/76877 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76892
摘要： The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.
摘要翻译：本发明涉及修复半导体衬底上的缺陷的方法。这是通过在空腔中的缺陷部分中选择性地沉积导电材料而实现的，同时从衬底的场区域去除残余部分。根据本发明的另一种方法包括在衬底的顶表面上形成均匀的导电材料覆盖层。本发明还公开了一种在衬底的第一导电材料上沉积第二导电材料的方法。

47. 发明授权

US09634412B2 Connector structures and methods 有权
公开(公告)号：US09634412B2
公开(公告)日：2017-04-25
申请号：US13183920
申请日：2011-07-15
申请人： Cyprian Uzoh , Craig Mitchell
发明人： Cyprian Uzoh , Craig Mitchell
IPC分类号： H05K1/09 , H01R13/03 , H05K3/40 , H05K3/28
CPC分类号： H01R13/03 , H05K1/09 , H05K3/282 , H05K3/4007 , H05K2201/0338 , H05K2201/09745 , Y10T29/49155
摘要： Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use.

48. 发明授权

US09142508B2 Single exposure in multi-damascene process 有权
标题翻译：在多镶嵌过程中单次曝光
公开(公告)号：US09142508B2
公开(公告)日：2015-09-22
申请号：US13170095
申请日：2011-06-27
申请人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
发明人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/52 , H01L23/528 , H01L23/532 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76834 , H01L21/76852 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53238 , H01L23/53252 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.
摘要翻译：仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。该方法可以包括在不同的去除条件下从多层结构去除材料。还公开了具有不同尺寸的多个空腔的多层镶嵌结构。空腔可以具有平滑的内壁表面。结构的层可以直接接触。空腔可以用导电金属或绝缘体填充。进一步公开了使用这些方法和结构的多层半导体器件。

49. 发明授权

US08692118B2 Reliable wire structure and method 有权
标题翻译：可靠的导线结构和方法
公开(公告)号：US08692118B2
公开(公告)日：2014-04-08
申请号：US13168675
申请日：2011-06-24
申请人： Cyprian Uzoh , Craig Mitchell
发明人： Cyprian Uzoh , Craig Mitchell
IPC分类号： H01B5/00
CPC分类号： H01B13/0036 , H01L24/43 , H01L24/45 , H01L2224/43 , H01L2224/43848 , H01L2224/45015 , H01L2224/45105 , H01L2224/45109 , H01L2224/45111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45157 , H01L2224/4516 , H01L2224/45163 , H01L2224/4518 , H01L2224/45184 , H01L2224/45565 , H01L2224/45572 , H01L2224/45573 , H01L2224/45605 , H01L2224/45609 , H01L2224/45611 , H01L2224/45644 , H01L2224/45647 , H01L2224/45655 , H01L2224/45657 , H01L2224/4568 , H01L2224/45686 , H01L2224/45693 , H01L2224/45887 , H01L2224/45893 , H01L2224/48 , H01L2224/85207 , H01L2924/01015 , H01L2924/10253 , Y10T29/49117 , H01L2924/01074 , H01L2924/00014 , H01L2924/0132 , H01L2924/00 , H01L2924/013 , H01L2924/04642 , H01L2924/0503 , H01L2924/01005 , H01L2924/01006
摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.
摘要翻译：公开了一种可被配置用于半导体器件的导线结构。线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。包层可以是导体。在各个方面，包覆层和芯具有不同的晶粒尺寸。芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。包覆层可以是在其厚度上具有不同浓度的次要组分的合金。还公开了形成线结构的方法。

50. 发明申请

US20130026645A1 LOW STRESS VIAS 有权
标题翻译：低应力VIAS
公开(公告)号：US20130026645A1
公开(公告)日：2013-01-31
申请号：US13193814
申请日：2011-07-29
申请人： Ilyas Mohammed , Belgacem Haba , Cyprian Uzoh
发明人： Ilyas Mohammed , Belgacem Haba , Cyprian Uzoh
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L23/5226 , H01L21/76898 , H01L23/481 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2224/10135 , H01L2924/07811 , H01L2924/00
摘要： A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
摘要翻译：部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。第二金属区域可具有大于第一金属层的CTE的CTE。导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

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