专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US4464754A Memory system with redundancy for error avoidance 失效
标题翻译：具有冗余的存储系统，用于避免错误
公开(公告)号：US4464754A
公开(公告)日：1984-08-07
申请号：US362462
申请日：1982-03-26
申请人： Roger G. Stewart , Andrew G. F. Dingwall
发明人： Roger G. Stewart , Andrew G. F. Dingwall
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G11C29/74 , G06F11/1008 , G06F11/1076
摘要： A memory system in which two or more memory modules containing the same information have their respective data outputs connected to the same data line. Each module includes means for checking the parity of the data being read-out at its output and in the event of a parity error indication effectively disconnects its output from the data line.
摘要翻译：其中包含相同信息的两个或更多个存储器模块具有连接到相同数据线的各自的数据输出的存储器系统。每个模块包括用于在其输出处检查正在读出的数据的奇偶校验以及在奇偶校验错误指示的情况下有效地将其输出与数据线断开的装置。

42. 发明授权

US08350588B2 Deactivation of integrated circuits 有权
标题翻译：集成电路的停用
公开(公告)号：US08350588B2
公开(公告)日：2013-01-08
申请号：US13079754
申请日：2011-04-04
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： H03K19/00
CPC分类号： H03K19/173 , G06F21/35 , G06F21/6209 , G06F21/77 , G06F2221/2143 , G06F2221/2147 , G06K19/07309
摘要： Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated from a substrate, is placed into an electromagnetic field of sufficient power to erase or reprogram the erasable non-volatile memory. The entire integrated circuit is permanently disabled by erasing, altering, or reprogramming the erasable non-volatile memory. In preferred embodiments, the integrated circuit comprises a non-erasable non-volatile memory storing the activation code, and circuitry adapted to permanently disable the integrated circuit when the code in the erasable non-volatile memory does not match the activation code in the non-erasable non-volatile memory. Erasing, altering, or reprogramming the erasable non-volatile memory results in a mismatch of the non-volatile memories, which permanently deactivates the integrated circuit.
摘要翻译：公开了永久禁用集成电路的集成电路和方法。一种具有可擦除非易失性存储器的集成电路，其适于存储当可擦除非易失性存储器中的代码在与基板分离之后被改变或擦除时禁用集成电路的激活码和逻辑，具有足够功率以消除或重新编程可擦除非易失性存储器的电磁场。整个集成电路通过擦除，更改或重新编程可擦除的非易失性存储器而永久禁用。在优选实施例中，集成电路包括存储激活码的不可擦除非易失性存储器，以及适于在可擦除非易失性存储器中的代码与非易失性存储器中的激活码不匹配时永久禁用集成电路的电路，可擦除非易失性存储器。擦除，改变或重新编程可擦除的非易失性存储器会导致永久停用集成电路的非易失性存储器的不匹配。

43. 发明授权

US08059478B2 Low cost testing and sorting for integrated circuits 有权
标题翻译：集成电路的低成本测试和排序
公开(公告)号：US08059478B2
公开(公告)日：2011-11-15
申请号：US12328675
申请日：2008-12-04
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C29/38 , G11C2029/4002
摘要： Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.
摘要翻译：公开了集群中集成电路的测试和分类方法。每个集群的电源和数据终端连接到公共电源和数据总线，提供公共电源。每个集成电路具有存储激活码的第一非易失性存储器和能够存储激活码的第二可编程非易失性存储器。如果集成电路通过测试，则将存储在第一非易失性存储器中的激活码写入第二非易失性存储器。如果第一和第二非易失性存储器中的代码匹配，则与集群分离时，集成电路是独立的。分离后，查询集成电路以确定哪些响应。每个集成电路包括适于确定第一和第二非易失性存储器中的代码是否匹配的逻辑。如果代码不匹配，则与集群分离时，逻辑将永久禁用集成电路。

44. 发明授权

US08056818B2 Integrated circuits with persistent data storage 有权
标题翻译：具有持久数据存储的集成电路
公开(公告)号：US08056818B2
公开(公告)日：2011-11-15
申请号：US12111140
申请日：2008-04-28
申请人： Roger G. Stewart , John Rolin
发明人： Roger G. Stewart , John Rolin
IPC分类号： G06K19/06
CPC分类号： G06K19/0723 , G06K7/10019 , G06K19/07381
摘要： The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.
摘要翻译：在本发明中引入的电路选择性地减慢保持特定状态长时间的电子电路的功能。该电路不仅用于在维护电子窃贼试图绕过代码的安全性方面实现期望的效果，而且在其他应用中，例如使电路在短暂的功率损失的情况下继续工作。例如，在RFID系统中，如果读取器跳频，当读取器改变到其他频率时，标签失去长达约400毫秒的功率。在优选实施例中，所公开的电路与破坏序列结合使用。

45. 发明授权

US07377445B1 Integrated circuits with persistent data storage 有权
公开(公告)号：US07377445B1
公开(公告)日：2008-05-27
申请号：US11264573
申请日：2005-10-31
申请人： Roger G. Stewart , John Rolin
发明人： Roger G. Stewart , John Rolin
IPC分类号： G06K19/00
CPC分类号： G06K19/0723 , G06K7/10019 , G06K19/07381
摘要： The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit by maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.

46. 发明授权

US07364084B2 Integrated circuits with persistent data storage 有权
标题翻译：具有持久数据存储的集成电路
公开(公告)号：US07364084B2
公开(公告)日：2008-04-29
申请号：US11153030
申请日：2005-06-14
申请人： Roger G. Stewart , John Rolin
发明人： Roger G. Stewart , John Rolin
IPC分类号： G06K19/00
CPC分类号： G06K19/07381 , G06K19/0723
摘要： The circuitry introduced in this invention selectively slows down the functioning of an electronic circuit by maintaining a particular state for a prolonged period of time. This circuitry is used not only to achieve the desired effect in maintaining security from electronic thieves trying to circumvent codes but also in other applications such as enabling a circuit to continue to function in the event of a brief loss of power. For example, in an RFID system, if a reader is frequency hopping, a tag loses power for as long as about 400 milliseconds when the reader changes to other frequencies. In a preferred embodiment, the disclosed circuitry is used in conjunction with a destruct sequence.
摘要翻译：在本发明中引入的电路通过长时间维持特定状态来选择性地减慢电子电路的功能。该电路不仅用于在维护电子窃贼试图绕过代码的安全性方面实现期望的效果，而且在其他应用中，例如使电路在短暂的功率损失的情况下继续工作。例如，在RFID系统中，如果读取器跳频，当读取器改变到其他频率时，标签失去长达约400毫秒的功率。在优选实施例中，所公开的电路与破坏序列结合使用。

47. 发明授权

US06417825B1 Analog active matrix emissive display 有权
标题翻译：模拟有源矩阵发射显示
公开(公告)号：US06417825B1
公开(公告)日：2002-07-09
申请号：US09200513
申请日：1998-11-25
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G09G330
CPC分类号： G09G3/30 , G09G3/2011 , G09G3/2018 , G09G3/2051 , G09G2300/0809 , G09G2300/0842
摘要： An emissive display device such as an active matrix electroluminescent display (AMEL display) has an improved method of operation. The AMEL display produces gray scale operation comprising an array of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line, and its drain connected to the gate of a second transistor. The second transistor has its source adapted to receive a ramped voltage level, and its drain connected to a first electrode of an electroluminescent cell. The electroluminescent cell has a second electrode connected to an alternating current high voltage power source, wherein the electroluminescent cell is illuminated, when the ramp voltage level is less than a voltage level on the gate of the second transistor. The ramp voltage level is increased linearly during a frame duration, and the alternating current high voltage power source is on continuously during the same frame duration. The alternating current high voltage power source may also be varied in amplitude from a minimum peak-to-peak value to a maximum peak-to-peak value during the frame duration.
摘要翻译：诸如有源矩阵电致发光显示器（AMEL显示器）的发射显示装置具有改进的操作方法。 AMEL显示器产生包括像素阵列的灰度级操作，每个像素包括其栅极连接到选择线的第一晶体管，其源极连接到数据线，其漏极连接到第二晶体管的栅极。第二晶体管的源极适于接收斜坡电压电平，其漏极连接到电致发光单元的第一电极。电致发光单元具有连接到交流高压电源的第二电极，其中当斜坡电压电平小于第二晶体管的栅极上的电压电平时，电致发光单元被照亮。斜坡电压电平在帧持续时间内线性增加，并且交流电压高电压电源在相同的帧持续时间期间连续地连续。在帧持续时间期间，交流电压高压电源也可以从最小峰 - 峰值到最大峰 - 峰值的幅度变化。

48. 发明授权

US5122676A Variable pulse width generator including a timer vernier 失效
标题翻译：可变脉冲宽度发生器，包括定时器VERNIER
公开(公告)号：US5122676A
公开(公告)日：1992-06-16
申请号：US620681
申请日：1990-12-03
申请人： Roger G. Stewart , George R. Briggs
发明人： Roger G. Stewart , George R. Briggs
IPC分类号： G09G3/20 , G09G3/36 , H03M1/82
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0259 , G09G2310/027
摘要： A pulse logic circuit comprises a plurality of interconnected stages. Each of the stages includes a relatively large node-charging transistor which, when enabled, forwards charging current to a node from a timing pulse of one of a plurality of phases applied to a load capacitance in series with the node-charging transistor. Such large transistors exhibit significant gate-to-source and gate-to drain distributed capacitances. The response time for charging a selected stage node can be decreased by precharging the gate of the node-charging transistor of a selected stage to enable the transistor prior to the application of a timing pulse, thereby increasing the maximum operating speed of the circuit. Disclosed species of such a pulse logic circuit include time vernier circuits which can be utilized as control circuitry for a liquid crystal television or computer display.
摘要翻译：脉冲逻辑电路包括多个互连级。每个级包括相对较大的节点充电晶体管，其在使能时，从施加到与节点充电晶体管串联的负载电容的多个相中的一个相的定时脉冲向节点转发充电电流。这种大型晶体管表现出显着的栅极到源极和栅极到漏极分布电容。通过对选定级的节点充电晶体管的栅极进行预充电，可以在施加定时脉冲之前使晶体管使能，从而提高电路的最大工作速度，可以减小对选定级节点充电的响应时间。这种脉冲逻辑电路的公开物种包括可用作液晶电视或计算机显示器的控制电路的时间游标电路。

49. 发明授权

US5076667A High speed signal and power supply bussing for liquid crystal displays 失效
标题翻译：液晶显示器的高速信号和电源总线
公开(公告)号：US5076667A
公开(公告)日：1991-12-31
申请号：US471566
申请日：1990-01-29
申请人： Roger G. Stewart , Alfred C. Ipri
发明人： Roger G. Stewart , Alfred C. Ipri
IPC分类号： G02F1/1345
CPC分类号： G02F1/1345
摘要： A Liquid Crystal Display device has first and second transparent substrates with a liquid crystal material sealed therebetween; a centrally disposed optically active display region having a matrix of pixels and a first and second scanner, and a transparent common electrode formed on the inner surface of the first and second transparent substrates, respectively; and a power supply and data signal distribution region surrounding at least a portion of the optically active display region and near the first and second scanners. The power supply and data signal distribution region comprises (a) a groove, and (b) a plurality of parallel conductors, formed on the inner surface of the second and first transparent substrates, respectively, which conductors include a height extending into the groove to reduce each conductor's resistance. Conductor capacitance is reduced by (a) eliminating the transparent common electrode from the groove, and/or (b) providing an inert dielectric material or gas in the distribution region with a lower dielectric constant than the liquid crystal material.
摘要翻译：液晶显示装置具有密封在其间的液晶材料的第一和第二透明基板; 分别具有像素矩阵和第一和第二扫描仪的中心布置的光学活性显示区域和分别形成在第一和第二透明基板的内表面上的透明公共电极; 以及围绕光学活动显示区域的至少一部分并且靠近第一和第二扫描器的电源和数据信号分配区域。电源和数据信号分配区域包括（a）分别形成在第二和第一透明基板的内表面上的凹槽和（b）多个平行导体，该导体包括延伸到凹槽中的高度减少每个导线的电阻。通过（a）从沟槽去除透明公共电极，和/或（b）在分布区域中提供比液晶材料低的介电常数的惰性电介质材料或气体来减小导体电容。

50. 发明授权

US4968119A High-density liquid-crystal active dot-matrix display structure 失效
标题翻译：高密度液晶有源点阵显示结构
公开(公告)号：US4968119A
公开(公告)日：1990-11-06
申请号：US295416
申请日：1989-01-10
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G02F1/136 , G02F1/1368 , G09F9/30
CPC分类号： G02F1/1368
摘要： A liquid-crystal active dot-matrix display structure comprised of an array of pixel cells, which is implementable in integrated-circuit form, employs a spatial configuration for the respective pixel cells, each of which includes (1) a liquid-crystal element, (2) data line, (3) select line, and (4) drive-transistor, that both increases the proportion of the display-structure area occupied by the liquid-crystal elements themselves and also reduces parasitic capacitance, with respect to the spatial configurations employed by the prior art. The result is a brighter display that is particularly suitable for high-density displays (e.g., 1000 lines per inch in each dimension).
摘要翻译：由可以集成电路形式实现的像素单元阵列构成的液晶有源点阵显示结构采用各自像素单元的空间配置，每个像素单元包括（1）液晶元件，（2）数据线，（3）选择线，和（4）驱动晶体管，这两者都增加了液晶元件本身所占据的显示结构面积的比例，并且相对于空间现有技术采用的结构。结果是特别适用于高密度显示器（例如，每个尺寸的每英寸1000线）的更亮的显示器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式