专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US08259525B2 Using a bit specific reference level to read a memory 有权
标题翻译：使用特定的参考级别读取内存
公开(公告)号：US08259525B2
公开(公告)日：2012-09-04
申请号：US13353531
申请日：2012-01-19
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
摘要翻译：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。在一些实施例中，可以改善所得到的读取窗口或边缘。

42. 发明申请

US20110113303A1 METHOD AND APPARATUSES FOR CUSTOMIZABLE ERROR CORRECTION OF MEMORY 有权
标题翻译：用于存储器可定制错误校正的方法和装置
公开(公告)号：US20110113303A1
公开(公告)日：2011-05-12
申请号：US12617661
申请日：2009-11-12
申请人： Ferdinando Bedeschi , Paolo Amato , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Paolo Amato , Roberto Gastaldi
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： Described herein are a method and apparatuses for providing customizable error correction for memory arrays. In one embodiment, an apparatus includes a memory device having a memory array to store data and an analog to digital sense unit coupled to the memory array. The analog to digital sense unit senses analog signals associated with the memory array and converts the analog signals into distributions of digital values. An error-correcting code (ECC) unit receives the distributions of digital values from the analog to digital sense unit. A configurable non-volatile look-up table generates ECC parameters including error probability data and provides the ECC parameters to the ECC unit for error correction. The error probability data has error probability values that are associated with the distributions of digital values. The ECC unit executes an ECC algorithm to provide error correction using the error probability data.
摘要翻译：这里描述了一种用于为存储器阵列提供可定制的纠错的方法和装置。在一个实施例中，装置包括具有用于存储数据的存储器阵列和耦合到存储器阵列的模拟到数字感测单元的存储器件。模拟到数字感测单元感测与存储器阵列相关联的模拟信号，并将模拟信号转换成数字值的分布。纠错码（ECC）单元接收从模拟到数字感测单元的数字值的分布。可配置的非易失性查找表生成包括错误概率数据的ECC参数，并将ECC参数提供给ECC单元用于纠错。误差概率数据具有与数字值分布相关联的误差概率值。 ECC单元执行ECC算法以使用错误概率数据提供纠错。

43. 发明授权

US07563684B2 Process for manufacturing an array of cells including selection bipolar junction transistors 有权
标题翻译：用于制造包括选择双极结型晶体管的单元阵列的工艺
公开(公告)号：US07563684B2
公开(公告)日：2009-07-21
申请号：US11264084
申请日：2005-11-01
申请人： Fabio Pellizzer , Giulio Casagrande , Roberto Gastaldi , Loris Vendrame , Augusto Benvenuti , Tyler Lowrey
发明人： Fabio Pellizzer , Giulio Casagrande , Roberto Gastaldi , Loris Vendrame , Augusto Benvenuti , Tyler Lowrey
IPC分类号： H01L21/8226
CPC分类号： H01L29/685 , H01L27/101 , H01L27/24
摘要： A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.
摘要翻译：一种用于制造单元阵列的方法，包括：在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口，从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口，由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件，每个存储部件具有连接到相应的第二传导区域的端子。

44. 发明申请

US20090116281A1 Reading Phase Change Memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US20090116281A1
公开(公告)日：2009-05-07
申请号：US12354425
申请日：2009-01-15
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

45. 发明授权

US07495944B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US07495944B2
公开(公告)日：2009-02-24
申请号：US11093878
申请日：2005-03-30
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

46. 发明申请

US20070019465A1 Detecting switching of access elements of phase change memory cells 有权
标题翻译：检测相变存储单元存取单元的切换
公开(公告)号：US20070019465A1
公开(公告)日：2007-01-25
申请号：US11527147
申请日：2006-09-26
申请人： Ferdinando Bedeschi , Claudio Resta , Ward Parkinson , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Claudio Resta , Ward Parkinson , Roberto Gastaldi
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C7/062 , G11C7/08 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054 , G11C2013/0071 , G11C2213/76
摘要： A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.
摘要翻译：存储器包括由相变材料制成的用于存储逻辑值的存储元件（OUM）和响应于存储单元的选择从较高电阻状态切换到较低电阻状态的存取元件（OTS），较高电阻条件下的存取元件将存储元件与读取电路分离，并将该存储元件耦合到读取电路的较低电阻条件。读取电路包括读出放大器，用于根据与存储器单元相关联的电量确定存储单元中存储的逻辑值。读取电路还包括检测器，其通过与延迟波形进行比较来检测接入元件的切换，或者检测列变化率的变化;以及电路，用于响应于检测到的切换访问元素

47. 发明申请

US20060221712A1 Using a bit specific reference level to read a memory 有权
标题翻译：使用特定的参考级别读取内存
公开(公告)号：US20060221712A1
公开(公告)日：2006-10-05
申请号：US11093877
申请日：2005-03-30
申请人： Tyler Lowrey , Ward Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C7/10
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
摘要翻译：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。在一些实施例中，可以改善所得到的读取窗口或边缘。

48. 发明申请

US20060049392A1 Process for manufacturing an array of cells including selection bipolar junction transistors 有权
公开(公告)号：US20060049392A1
公开(公告)日：2006-03-09
申请号：US11264084
申请日：2005-11-01
申请人： Fabio Pellizzer , Giulio Casagrande , Roberto Gastaldi , Loris Vendrame , Augusto Benvenuti , Tyler Lowrey
发明人： Fabio Pellizzer , Giulio Casagrande , Roberto Gastaldi , Loris Vendrame , Augusto Benvenuti , Tyler Lowrey
IPC分类号： H01L29/06
CPC分类号： H01L29/685 , H01L27/101 , H01L27/24
摘要： A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

49. 发明授权

US4888497A Generator of reset pulses upon the rise of the power supply for CMOS-type integrated circuits 失效
标题翻译： CMOS型集成电路电源上升时的复位脉冲发生器
公开(公告)号：US4888497A
公开(公告)日：1989-12-19
申请号：US187581
申请日：1988-04-28
申请人： Marco Dallabora , Roberto Gastaldi , David Novosel
发明人： Marco Dallabora , Roberto Gastaldi , David Novosel
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： The generator has an input stage (I) including a voltage divider for dividing the voltage between the power supply and the ground, having a node constituting the output of the input stage, and by a positive-feedback threshold loop, driven by another node of the voltage divider to make the voltage in the output node rise sharply when the voltage in the other node exceeds a threshold. A first Schmitt trigger (T1) is driven by the voltage rise front supplied by the input stage; and a former of output pulses (F) comprising a second Schmitt trigger (T2) is driven by circuit means adapted to directly apply to the second Schmitt trigger the voltage front arriving from the first Schmitt trigger and to restore the original voltage level with a preset delay.

50. 发明授权

US08638605B2 Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells 有权
标题翻译：装置和方法包括耦合到一串存储器单元的双极结型晶体管
公开(公告)号：US08638605B2
公开(公告)日：2014-01-28
申请号：US13115786
申请日：2011-05-25
申请人： Paolo Tessariol , Roberto Gastaldi
发明人： Paolo Tessariol , Roberto Gastaldi
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
摘要翻译：一些实施例包括具有一串存储器单元的装置和方法，导体线路和双极结型晶体管，被配置为选择性地将该串存储器单元耦合到导电线路。描述包括附加装置和方法的其它实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式