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41. 发明授权

US07065086B2 Method and system for efficient layer 3-layer 7 routing of internet protocol (“IP”) fragments 有权
标题翻译：网络协议（“IP”）片段的有效层3层7路由的方法和系统
公开(公告)号：US07065086B2
公开(公告)日：2006-06-20
申请号：US09931206
申请日：2001-08-16
申请人： Claude Basso , Jean Louis Calvignac , Philippe Damon , Gordon Taylor Davis
发明人： Claude Basso , Jean Louis Calvignac , Philippe Damon , Gordon Taylor Davis
IPC分类号： H04L12/28
CPC分类号： H04L49/25 , H04L49/602
摘要： According to the present invention there is provided to a method and system for efficiently routing IP fragments (i.e., datagrams) at layer 3 through layer 7 of the OSI model without reassembling the fragments. Time-consuming reassembly of fragments of a datagram at higher layers that would be required via conventional methods is avoided, thereby improving processing speed of fragments and utilizing fewer resources for processing fragments of a datagram than would be required during reassembly of the fragments via conventional methods. The method and system route a datagram that has been fragmented into a plurality of fragments utilizing content-based routing information included in one or more fragments of the plurality of fragments, comprising: generating a context for the datagram associated with routing the plurality of fragments of the datagram and setting the context for the datagram to passive until content-based routing information included in the one or more fragments is received; caching received fragments while the context is set to passive; determining a destination for routing the plurality of fragments when content-based routing information included in the one or more fragments is received and setting the context for the datagram to active; and routing any cached fragments and subsequently received fragments of the datagram to the determined destination while the context is active without reassembling the plurality of fragments into the datagram. Additionally, a router and server load balancer incorporating the present invention are provided.
摘要翻译：根据本发明，提供了一种用于在不重新组装片段的情况下有效地路由OSI模型的层3到层7的IP片段（即，数据报）的方法和系统。避免了通过常规方法需要的较高层数据报片段的重新组装，从而提高片段的处理速度，并利用较少的资源来处理数据报的片段，而不是通过常规方法重新组装片段时所需要的数据报片段。所述方法和系统使用包括在所述多个片段中的一个或多个片段中的基于内容的路由信息将已经被分段的数据报路由到多个片段中，包括：生成与路由多个片段的多个片段相关联的数据报的上下文数据报并将数据报的上下文设置为被动，直到接收到包含在一个或多个片段中的基于内容的路由信息为止; 缓存接收到的片段，同时将上下文设置为被动; 当接收到包含在所述一个或多个片段中的基于内容的路由信息被接收并且将所述数据报的上下文设置为活动时，确定用于路由所述多个片段的目的地; 并且在上下文是活动的情况下将任何高速缓存的分段和随后接收的数据报的片段路由到所确定的目的地，而不将多个片段重新组合到数据报中。另外，提供并入本发明的路由器和服务器负载均衡器。

42. 发明授权

US06298340B1 System and method and computer program for filtering using tree structure 失效
标题翻译：使用树结构进行过滤的系统和方法以及计算机程序
公开(公告)号：US06298340B1
公开(公告)日：2001-10-02
申请号：US09312148
申请日：1999-05-14
申请人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
发明人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , Y10S707/99931 , Y10S707/99933 , Y10S707/99943 , Y10S707/99944
摘要： A classification system includes a software managed tree testing bits from a key which labels an item. The bits are chosen by application of the Choice Bit Algorithm to the Rules in a Database of Rules. A controller including logic parses an unknown Key for bits to be tested in the decision nodes of a binary tree. Tests dictated by the tree are conducted in a predetermined way until all but one Rule from the database or all but a few Rules from the database are eliminated from consideration, whereupon the Key is fully tested by the one remaining Rule or in a lattice constructed of the remaining plurality of Rules, to determine an action to enforce on the item. Certain compare tests are used in the binary tree for the case that otherwise identical or similar rules are applied to integer ranges of key values which do not fall upon power of 2 boundaries. Furthermore, some very frequently occurring rules in such final tests might be designated as secondary rules, the remaining rules designated as primary rules, the entire decision tree recalculated using only primary rules, and the primary rules then connected to secondary rules only when logically necessary by means of a system of pointers making use of relative priorities of rules.
摘要翻译：分类系统包括从标签项目的键的软件管理树测试位。通过将选择位算法应用于规则数据库中的规则来选择位。包含逻辑的控制器在二叉树的决策节点中解析要测试的位的未知密钥。由树进行的测试以预定的方式进行，直到从数据库中除了一个规则之外的所有除了数据库中的所有规则或从数据库中除了少数几个规则之外的所有测试都被消除，由此Key被完整的一个规则或由剩余的多个规则，以确定对该项目执行的操作。在二叉树中使用某些比较测试，否则相同或相似的规则应用于不落在2边界的幂的关键值的整数范围。此外，这些最终测试中的一些非常频繁出现的规则可能被指定为次要规则，剩余的规则被指定为主要规则，仅使用主要规则重新计算的整个决策树，然后仅在逻辑上必要时连接到次级规则的主要规则使用指针的相对优先级的指针系统的手段。

43. 发明授权

US07620048B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07620048B2
公开(公告)日：2009-11-17
申请号：US11152419
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
摘要翻译：公开了用于在通信系统中传送控制信息的装置。该装置包括网络处理器，可操作地耦合到网络处理器的控制点处理器以及由控制点处理器生成的引导帧。引导帧包括其中放置帧控制信息的第一部分，并且被网络处理器用于更新网络处理器内的至少一个控制寄存器; 第二部分，承载由控制点处理器分配的相关器，以将引导的帧响应与其请求相关联; 第三部分承载一个或一系列指导命令; 和一个结束分隔符引导命令。

44. 发明授权

US07590057B2 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07590057B2
公开(公告)日：2009-09-15
申请号：US11152453
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.
摘要翻译：控制子系统，多个接口处理器，多个媒体接口，多个队列可操作地耦合并且响应于控制信号将数据从存储器移动到多个队列中的所选择的一个队列。

45. 发明授权

US07257616B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07257616B2
公开(公告)日：2007-08-14
申请号：US11152119
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

46. 发明授权

US07123622B2 Method and system for network processor scheduling based on service levels 失效
公开(公告)号：US07123622B2
公开(公告)日：2006-10-17
申请号：US09834141
申请日：2001-04-12
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/32 , H04L47/20 , H04L47/2441 , H04L47/28 , H04L47/36 , H04L47/50 , H04L47/58 , H04L47/60 , H04L47/62 , H04L47/623
摘要： A system and method of moving information units from an output flow control toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on a weighted fair queue where position in the queue is adjusted after each service based on a weight factor and the length of frame, a process which provides a method for and system of interaction between different calendar types is used to provide minimum bandwidth, best effort bandwidth, weighted fair queuing service, best effort peak bandwidth, and maximum burst size specifications. The present invention permits different combinations of service that can be used to create different QoS specifications. The “base” services which are offered to a customer in the example described in this patent application are minimum bandwidth, best effort, peak and maximum burst size (or MBS), which may be combined as desired. For example, a user could specify minimum bandwidth plus best effort additional bandwidth and the system would provide this capability by putting the flow queue in both the NLS and WFQ calendar. The system includes tests when a flow queue is in multiple calendars to determine when it must come out.

47. 发明授权

US07072347B2 Assignment of packet descriptor field positions in a network processor 失效
公开(公告)号：US07072347B2
公开(公告)日：2006-07-04
申请号：US09792494
申请日：2001-02-23
申请人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L49/901
摘要： A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

48. 发明授权

US06681364B1 Cyclic redundancy check for partitioned frames 失效
标题翻译：分区帧的循环冗余校验
公开(公告)号：US06681364B1
公开(公告)日：2004-01-20
申请号：US09405669
申请日：1999-09-24
申请人： Jean Louis Calvignac , Clark Debs Jeffries , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Clark Debs Jeffries , Fabrice Jean Verplanken
IPC分类号： H03M1300
CPC分类号： H04L1/0061 , H03M13/091 , H04L1/0071 , H04L1/0072
摘要： An improved method and system for generating a frame check sequence. A multiple-bit data string, M, is received in which M is of the form: anbncndnan−1bn−1cn−1dn−1 . . . a2b2c2d2a1b1c1d1. M is thereafter parsed into multiple subframes of the form: anan−1an−2 . . . a2a1; bnbn−1bn−2 . . . b2b1; cncn−1cn−2 . . . c2c1; and dndn−1dn−2 . . . d2d1. The subframes are padded with zeros resulting in subframes of the form: an000an−1000an−2000 . . . a2000a1000; 0bn000bn−1000bn−200 . . . 0b2000b100; 00cn000cn−1000cn−20 . . . 00c2000c100; and 000dn000dn−1000dn−2 . . . 000d2000d1. A partial check sum is then generated for each of the multiple subframes. Finally, each of the partial check sums are added together such that a frame check sequence for M is obtained.
摘要翻译：一种用于生成帧校验序列的改进的方法和系统。接收多位数据串M，其中M具有以下形式：M随后被解析为形式的多个子帧：并且子帧用零填充，产生以下形式的子帧：然后生成部分校验和对于多个子帧中的每一个。最后，将每个部分校验和相加在一起，从而获得用于M的帧校验序列。

49. 发明授权

US06647004B2 Network switch using network processor and methods 失效
公开(公告)号：US06647004B2
公开(公告)日：2003-11-11
申请号：US10003981
申请日：2001-10-23
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04B7216
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

50. 发明授权

US06460120B1 Network processor, memory organization and methods 失效
标题翻译：网络处理器，内存组织和方法
公开(公告)号：US06460120B1
公开(公告)日：2002-10-01
申请号：US09384744
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样的设备的方法，其中通过多个存储器元件和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。存储器元件和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令中与其它元件协作。存储元件的访问以特定方式和操作规则进行控制，这些规则由多个处理器提供对多个存储器元件的受控多次访问。

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