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41. 发明授权

US08212938B2 Sync signal acquisition device 有权
标题翻译：同步信号采集装置
公开(公告)号：US08212938B2
公开(公告)日：2012-07-03
申请号：US11822392
申请日：2007-07-05
申请人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
发明人： Jui-Yuan Tsai , Szu-Ping Chen , Yu-Pin Chou
IPC分类号： H04N9/72
CPC分类号： H04N5/08 , H04N5/185 , H04N9/44
摘要： A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
摘要翻译：公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

42. 发明授权

US07778321B2 Method for adjusting parameters of equalizer 有权
标题翻译：调整均衡器参数的方法
公开(公告)号：US07778321B2
公开(公告)日：2010-08-17
申请号：US11165029
申请日：2005-06-24
申请人： Yu-Pin Chou , Chao-Hsin Lu
发明人： Yu-Pin Chou , Chao-Hsin Lu
IPC分类号： H03K5/159
CPC分类号： H04L25/03019 , H04L2025/03764
摘要： A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.
摘要翻译：用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。首先，检测发送信号中的第一频带和第二频带的信号强度。然后比较第一频带和第二频带的信号强度以获得补偿比，即第一频带的总补偿量到第二频带。最后，根据补偿比的反馈调整均衡器的参数设置。因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

43. 发明申请

US20090153574A1 METHOD AND SYSTEM FOR UPDATING FIRMWARE 审中-公开
标题翻译：用于更新固件的方法和系统
公开(公告)号：US20090153574A1
公开(公告)日：2009-06-18
申请号：US12275912
申请日：2008-11-21
申请人： Yu-Pin Chou , Tzou-Bo Lin , Chih-Ming Lee , Ming-Syun Wu
发明人： Yu-Pin Chou , Tzou-Bo Lin , Chih-Ming Lee , Ming-Syun Wu
IPC分类号： G09G5/39
CPC分类号： G09G5/003 , G09G5/006 , G09G2370/047
摘要： A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I2C auxiliary channel device servicer for receiving the output signal and generating an I2C protocol updated firmware, and a memory unit for updating firmware according to the I2C protocol updated firmware. A method for updating firmware is also disclosed.
摘要翻译：通过DisplayPort接口更新固件的系统包括具有DisplayPort接口的源设备和具有DisplayPort接口的接收器设备。源设备包括用于存储和提供更新的固件的存储电路，以及用于以辅助信道信号格式输出更新的固件的源设备辅助通道。宿设备包括宿设备辅助通道，用于以辅助通道信号格式接收更新的固件，从而生成输出信号，用于接收输出信号并产生I2C协议更新固件的I2C辅助通道设备服务器，以及存储器单元根据I2C协议更新固件更新固件。还公开了一种用于更新固件的方法。

44. 发明授权

US07545222B2 Phase lock loop for rapid lock-in and method therefor 有权
标题翻译：锁相环快速锁定及其方法
公开(公告)号：US07545222B2
公开(公告)日：2009-06-09
申请号：US11620053
申请日：2007-01-05
申请人： Yu-Pin Chou , Chi-Kung Kuan
发明人： Yu-Pin Chou , Chi-Kung Kuan
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/0891 , H03L7/0991 , H03L7/0996 , H03L2207/06 , Y10S331/02
摘要： A phase-locked loop (PLL) for rapid lock-in applicable to digital, analog, or hybrid digital-analog PLL circuits is provided. Besides the units for basic operation, including a phase-frequency detector (PFD), a charge pump, a loop filter, and/or a voltage/current/digital-controlled oscillator (VCO/ICO/DCO), an additional lock-in actuator circuit is provided for providing lock-in signals, achieving the purpose of rapid lock-in through operational processes.
摘要翻译：提供了一种用于快速锁定的锁相环（PLL），适用于数字，模拟或混合数字 - 模拟PLL电路。除了用于基本操作的单元，包括相位频率检测器（PFD），电荷泵，环路滤波器和/或电压/电流/数字控制振荡器（VCO / ICO / DCO），附加锁定致动器电路被提供用于提供锁定信号，实现通过操作过程快速锁定的目的。

45. 发明授权

US07532028B2 Impedance matching circuit and related method thereof 有权
标题翻译：阻抗匹配电路及其相关方法
公开(公告)号：US07532028B2
公开(公告)日：2009-05-12
申请号：US11863286
申请日：2007-09-28
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： H03K17/16
CPC分类号： H03H7/40
摘要： The invention relates to an impedance matching circuit including: an input terminal for receiving an input signal; a variable impedance unit, coupled to the input terminal, having an equivalent impedance for providing the input terminal with an input impedance; a signal quality evaluating unit, coupled to the input terminal, for evaluating a signal quality of the input signal; and a control unit coupled to the variable impedance unit and the signal quality evaluating unit, for outputting a target control signal according to an evaluating result of the signal quality evaluating unit to adjust the equivalent impedance of the variable impedance unit.
摘要翻译：本发明涉及一种阻抗匹配电路，包括：输入端，用于接收输入信号; 耦合到输入端的可变阻抗单元具有用于向输入端提供输入阻抗的等效阻抗; 信号质量评估单元，耦合到输入端，用于评估输入信号的信号质量; 以及耦合到所述可变阻抗单元和所述信号质量评估单元的控制单元，用于根据所述信号质量评估单元的评估结果输出目标控制信号，以调整所述可变阻抗单元的等效阻抗。

46. 发明申请

US20080079511A1 IMPEDANCE MATCHING CIRCUIT AND RELATED METHOD THEREOF 有权
标题翻译：阻抗匹配电路及其相关方法
公开(公告)号：US20080079511A1
公开(公告)日：2008-04-03
申请号：US11863286
申请日：2007-09-28
申请人： Yu-Pin Chou
发明人： Yu-Pin Chou
IPC分类号： H03H7/40
CPC分类号： H03H7/40
摘要： The invention relates to an impedance matching circuit including: an input terminal for receiving an input signal; a variable impedance unit, coupled to the input terminal, having an equivalent impedance for providing the input terminal with an input impedance; a signal quality evaluating unit, coupled to the input terminal, for evaluating a signal quality of the input signal; and a control unit coupled to the variable impedance unit and the signal quality evaluating unit, for outputting a target control signal according to an evaluating result of the signal quality evaluating unit to adjust the equivalent impedance of the variable impedance unit.
摘要翻译：本发明涉及一种阻抗匹配电路，包括：输入端，用于接收输入信号; 耦合到输入端的可变阻抗单元具有用于向输入端提供输入阻抗的等效阻抗; 信号质量评估单元，耦合到输入端，用于评估输入信号的信号质量; 以及耦合到所述可变阻抗单元和所述信号质量评估单元的控制单元，用于根据所述信号质量评估单元的评估结果输出目标控制信号，以调整所述可变阻抗单元的等效阻抗。

47. 发明申请

US20080061854A1 APPARATUS AND RELATED METHOD FOR GENERATING OUTPUT CLOCK 有权
标题翻译：用于产生输出时钟的装置和相关方法
公开(公告)号：US20080061854A1
公开(公告)日：2008-03-13
申请号：US11847343
申请日：2007-08-30
申请人： Hsu-Jung Tung , Chi-Kung Kuan , Yu-Pin Chou
发明人： Hsu-Jung Tung , Chi-Kung Kuan , Yu-Pin Chou
IPC分类号： G06F1/04
CPC分类号： H04N7/56 , H04N5/04 , H04N5/126 , H04N5/602 , H04N21/2368 , H04N21/4305 , H04N21/4341 , H04N21/439
摘要： An apparatus for generating an audio output clock is disclosed. The apparatus at least includes a plurality of dividers and a frequency synthesizer. The apparatus utilizes the dividers to achieve dispersive frequency-division operations such that the anti-noise ability of the apparatus can be improved. In addition, the apparatus also utilizes dynamic phase adjustment to increase accuracy of the frequency of the audio output clock.
摘要翻译：公开了一种用于产生音频输出时钟的装置。该装置至少包括多个分频器和频率合成器。该装置利用分频器实现色散分频操作，从而可以提高装置的抗噪声能力。此外，该装置还利用动态相位调整来提高音频输出时钟频率的精度。

48. 发明授权

US07218261B2 Method of adjusting sampling condition of analog to digital converter and apparatus thereof 有权
标题翻译：调整模数转换器采样条件的方法及其装置
公开(公告)号：US07218261B2
公开(公告)日：2007-05-15
申请号：US11306638
申请日：2006-01-05
申请人： Jin-Sheng Gong , Yu-Pin Kuo , Yu-Pin Chou , Hung-Jen Chu
发明人： Jin-Sheng Gong , Yu-Pin Kuo , Yu-Pin Chou , Hung-Jen Chu
IPC分类号： H03M1/00
CPC分类号： H03M1/1245
摘要： A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.
摘要翻译：一种调整采样条件以在模数转换器中产生采样时钟的方法包括对模拟输入信号执行模数转换，从而产生具有多个采样的数字采样信号; 计算数字采样信号中两个相邻采样之间的差值; 将差值与阈值进行比较; 如果所述差值大于所述阈值，则将所述差值加到差值的和中; 并根据差值的和生成模数转换器的采样时钟。

49. 发明申请

US20060164551A1 ANALOG FRONT-END CIRCUIT FOR DIGITAL DISPLAYING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：用于数字显示设备的模拟前端电路及其控制方法
公开(公告)号：US20060164551A1
公开(公告)日：2006-07-27
申请号：US11279251
申请日：2006-04-11
申请人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
发明人： Chi-Feng Wang , Jui-Yuan Tsai , Yu-Pin Chou , Jin-Sheng Gong
IPC分类号： H03M1/12 , H04N5/14 , H04N5/05 , H04N9/455 , H04N9/64 , H04N5/45 , H04N9/44
CPC分类号： G09G5/04 , G09G3/2092
摘要： An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
摘要翻译：公开了一种数字显示器的模拟前端（AFE）电路，包括：第一电路，间歇地反转工作时钟以产生控制信号并产生采样信号，其中采样信号对应于工作时钟; 耦合到第一电路的第一模数转换器（ADC），用于根据采样信号将模拟视频信号转换成第一数字视频信号; 耦合到第一电路的第二模数转换器，用于根据采样信号将模拟视频信号转换成第二数字视频信号; 以及第一多路复用器，用于根据控制信号选择性地输出第一数字视频信号或第二数字视频信号。

50. 发明申请

US20050286626A1 Method for adjusting parameters of equalizer 有权
标题翻译：调整均衡器参数的方法
公开(公告)号：US20050286626A1
公开(公告)日：2005-12-29
申请号：US11165029
申请日：2005-06-24
申请人： Yu-Pin Chou , Chao-Hsin Lu
发明人： Yu-Pin Chou , Chao-Hsin Lu
IPC分类号： H03K5/159 , H04L27/01
CPC分类号： H04L25/03019 , H04L2025/03764
摘要： A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.
摘要翻译：用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。首先，检测发送信号中的第一频带和第二频带的信号强度。然后比较第一频带和第二频带的信号强度，以获得补偿比，即第一频带到第二频带的总补偿量。最后，根据补偿比的反馈调整均衡器的参数设置。因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

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