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    • 41. 发明授权
    • Efficient method to detect process induced defects in the gate stack of flash memory devices
    • 高效的方法来检测闪存器件的栅极堆叠中的工艺引起的缺陷
    • US06717850B1
    • 2004-04-06
    • US10313676
    • 2002-12-05
    • Jiang LiNian YangZhigang WangJohn Jianshi Wang
    • Jiang LiNian YangZhigang WangJohn Jianshi Wang
    • G11C1604
    • G11C29/50G11C16/04G11C2029/0403
    • A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.
    • 公开了一种处理半导体器件的方法,并且包括在闪存单元的栅极堆叠上施加相当高的电压一段时间。 然后,施加的电压的极性反转,并再次施加在栅极堆叠另外一段时间。 施加的电压大于用于存储器单元的通道擦除电压。 该施加的电压导致外部缺陷在栅极堆叠的氧化物/绝缘体层的界面处被放大。 然后,测试存储器单元(例如,通过测试电池),以便确定存储器单元是否有故障。 如果细胞有缺陷(例如,测试失败),则可以认为在存储单元中存在大量的外在缺陷并且被放大,导致测试失败。 如果单元通过测试,则可以认为存储单元基本上没有外在缺陷。 存储器单元/器件不良或可能被标记为有缺陷。
    • 44. 发明申请
    • METHOD AND APPARATUS FOR PROVIDING CONTEXT-BASED COUPON SHARING
    • 提供基于语境分析的方法和装置
    • US20140304085A1
    • 2014-10-09
    • US13992102
    • 2010-12-10
    • Dong LiuJiang LiHao YangZhanjiang Song
    • Dong LiuJiang LiHao YangZhanjiang Song
    • G06Q30/02
    • G06Q30/0269G06Q30/02
    • An approach is provided for context-based coupon sharing. A coupon management platform receives a request specifying an exchange of one or more coupons. The request includes, at least in part, one or more attribute-condition pairs associated with the one or more coupons, one or more participants of the exchange, or a combination thereof. The coupon management plat form determines context data associated with a first user, at least one device associated with the first user, at least one second user, at least one other device associated with the at least one second user, or a combination thereof. The coupon management platform then causes, at least in part, processing of the one or more attribute-condition pairs, the context data, or a combination thereof for initiating the exchange between the first user and the at least one second user.
    • 为基于上下文的优惠券共享提供了一种方法。 优惠券管理平台收到指定一个或多个优惠券交换的请求。 该请求至少部分地包括与一个或多个优惠券相关联的一个或多个属性条件对,交换的一个或多个参与者或其组合。 优惠券管理平台形式确定与第一用户相关联的上下文数据,与第一用户相关联的至少一个设备,至少一个第二用户,与至少一个第二用户相关联的至少一个其他设备或其组合。 优惠券管理平台至少部分地对一个或多个属性条件对,上下文数据或其组合进行处理,用于启动第一用户与至少一个第二用户之间的交换。
    • 46. 发明授权
    • Hybrid flash memory device
    • 混合闪存设备
    • US08560756B2
    • 2013-10-15
    • US11873810
    • 2007-10-17
    • Nian YangJiang LiFan Wan Lai
    • Nian YangJiang LiFan Wan Lai
    • G06F12/00
    • G06F12/0638G11C11/005G11C16/0408
    • A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage along with fast programming/erasure speeds and fast random access speeds.
    • 提供了混合存储器系统,其结合NAND闪存器件的优点与NOR闪存存储器件的优点。 该系统包括NAND闪速存储器部分,用于提供大容量存储和传统NAND闪速存储器件的快速编程/擦除能力。 该系统还包括NOR闪速存储器部分,以提供常规NOR闪存器件的代码存储和快速随机读取能力。 因此,混合存储器系统同时提供大容量存储和代码存储以及快速编程/擦除速度和快速随机存取速度。
    • 49. 发明授权
    • GaN semiconductor device having a high withstand voltage
    • 具有高耐压的GaN半导体器件
    • US08183597B2
    • 2012-05-22
    • US11568348
    • 2005-05-02
    • Nariaki IkedaJiang LiSeikoh Yoshida
    • Nariaki IkedaJiang LiSeikoh Yoshida
    • H01L31/06
    • H01L29/7787H01L29/2003
    • A GaN semiconductor device which has a low on-resistance, has a very small leak current when a reverse bias voltage is applied and is very excellent in withstand voltage characteristic, said GaN semiconductor device having a structure being provided with a III-V nitride semiconductor layer containing at least one hetero junction structure of III-V nitride semiconductors having different band gap energies; a first anode electrode arranged on a surface of said III-V nitride semiconductor by Schottky junction; a second anode electrode which is arranged on the surface of said III-V nitride semiconductor layer by Schottky junction, is electrically connected with said first anode electrode and forms a higher Schottky barrier than a Schottky barrier formed by said first anode electrode; and an insulating protection film which is brought into contact with said second anode electrode and is arranged on the surface of said III-V nitride semiconductor layer.
    • 具有低导通电阻的GaN半导体器件在施加反向偏置电压时具有非常小的漏电流并且具有非常优异的耐电压特性,所述GaN半导体器件具有设置有III-V族氮化物半导体 含有具有不同带隙能量的III-V族氮化物半导体的至少一种异质结结构的层; 通过肖特基结布置在所述III-V族氮化物半导体的表面上的第一阳极电极; 通过肖特基结布置在所述III-V族氮化物半导体层的表面上的第二阳极电极与所述第一阳极电连接,并形成比由所述第一阳极形成的肖特基势垒更高的肖特基势垒; 以及与所述第二阳极电极接触并设置在所述III-V族氮化物半导体层的表面上的绝缘保护膜。