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41. 发明授权

US6159813A Graded LDD implant process for sub-half-micron MOS devices 失效
公开(公告)号：US6159813A
公开(公告)日：2000-12-12
申请号：US819172
申请日：1997-03-17
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917 , H01L2924/00
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

42. 发明授权

US5605857A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
标题翻译：在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列
公开(公告)号：US5605857A
公开(公告)日：1997-02-25
申请号：US394546
申请日：1995-02-22
申请人： Mark Jost , Charles Dennison
发明人： Mark Jost , Charles Dennison
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/768 , H01L21/76877 , H01L27/10808 , H01L28/40 , H01L28/60 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , Y10S148/05
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于所述位线和所述另一有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和内部存储节点上表面。还公开了一种制造这种结构的方法。

43. 发明授权

US5250457A Method of forming a buried bit line array of memory cells 失效
标题翻译：形成存储器单元的掩埋位线阵列的方法
公开(公告)号：US5250457A
公开(公告)日：1993-10-05
申请号：US838549
申请日：1992-02-19
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/76801 , H01L21/76829 , H01L27/10808
摘要： A method of forming a buried bit line array of memory cells comprises: a) providing an array of word lines atop a semiconductor wafer; b) providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; c) providing a layer of first material (preferably polyimide) atop the wafer to a selected thickness; d) patterning and etching the layer of first material to define a pattern of buried bit line grooves for formation of buried bit lines therewithin, the bit line grooves having a first selected width; e) providing a layer of insulating material to a selected thickness atop the wafer over the patterned and etched layer of first material, the selected thickness of insulating material being less than half the first selected width, the layer of insulating material narrowing the bit line grooves to a smaller second width; f) providing bit line contact openings to second active regions within and at the bases of the second width bit line grooves; g) conductively doped polysilicon and on overlying higher conductive material are provided within the grooves for bit line formation; h) an array of capacitors are provided atop the wafer which electrically engage with first active regions.
摘要翻译：形成存储单元的掩埋位线阵列的方法包括：a）在半导体晶片的顶部提供字线阵列; b）提供关于字线的有源区域以限定存储单元FET的阵列，所述有源区域由用于与存储单元电容器电连接的第一有源区域和用于与位线电连接的第二有源区域限定; c）在晶片顶上提供一层第一材料（优选聚酰亚胺）至所选择的厚度; d）图案化和蚀刻第一材料层以限定用于在其中形成掩埋位线的掩埋位线槽的图案，所述位线槽具有第一选定宽度; e）在所述图案化和蚀刻的第一材料层上的所述晶片的顶部上提供绝缘材料层，所述绝缘材料的所选厚度小于所述第一选定宽度的一半，所述绝缘材料层使所述位线沟槽变窄到较小的第二宽度; f）向位于第二宽度位线槽的底部内和底部的第二有源区提供位线接触开口; g）导电掺杂的多晶硅和覆盖的较高导电材料设置在用于位线形成的凹槽内; h）在与第一有源区电接合的晶片顶上提供一组电容器。

44. 发明授权

US5206183A Method of forming a bit line over capacitor array of memory cells 失效
标题翻译：在存储器单元的电容器阵列上形成位线的方法
公开(公告)号：US5206183A
公开(公告)日：1993-04-27
申请号：US838537
申请日：1992-02-19
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76885 , H01L21/76889 , H01L28/40
摘要： A method of forming a bit line over capacitor array of memory cells includes providing a first layer of polyimide over word lines. Such layer is then patterned and etched to define storage node circuits. A first layer of conductively doped polysilicon is applied over the first layer of polyimide. A second layer of polyimide is applied over the first layer of conductively doped polysilicon. The second layer of polyimide and first layer of polysilicon are etched over the first layer of polyimide to define isolated cell storage nodes. Such can be conducted without any prior patterning or masking of the second layer of polyimide and first layer of polysilicon. A third layer of polyimide is provided atop the wafer over the isolated cell storage nodes. The third and first layers of polyimide are etched to define bit line contacts. Insulating spacers are provided about the periphery within the bit line contacts. Conductive material is deposited to provide conductive material pillars within the bit line contacts. Remaining portions of the first, second and third layers of polyimide are etched from the wafer. A capacitor cell dielectric layer is provided atop the individual storage nodes. A capacitor cell polysilicon layer is provided atop the capacitor cell dielectric layer to define an array of memory cell capacitors. An insulating layer is provided atop the cell polysilicon later. An array of digit lines are provided atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.
摘要翻译：在存储器单元的电容器阵列上形成位线的方法包括在字线上提供第一层聚酰亚胺。然后对该层进行图案化和蚀刻以定义存储节点电路。在第一层聚酰亚胺上施加第一层导电掺杂多晶硅。在第一层导电掺杂多晶硅上施加第二层聚酰亚胺。在第一层聚酰亚胺上蚀刻第二层聚酰亚胺和第一层多晶硅以限定隔离的电池存储节点。这样可以不进行第二层聚酰亚胺和第一多晶硅层的任何先前的图案化或掩蔽来进行。在隔离的电池存储节点上的晶片顶部提供第三层聚酰亚胺。蚀刻第三层和第一层聚酰亚胺以限定位线接触。围绕位线接触件周围的绝缘垫片设置。导电材料被沉积以在位线触点内提供导电材料柱。从晶片上蚀刻第一层，第二层和第三层聚酰亚胺的剩余部分。电容器单元电介质层设置在各个存储节点的顶部。电容器单元多晶硅层设置在电容器电介质层顶部以限定存储单元电容器阵列。之后在单元多晶硅顶上提供绝缘层。在晶片顶部提供数字线阵列，其电连接到电池电容器正上方的导电材料柱。

45. 发明申请

US20060273459A1 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 审中-公开
公开(公告)号：US20060273459A1
公开(公告)日：2006-12-07
申请号：US11496843
申请日：2006-07-31
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

46. 发明申请

US20060054996A1 Controlled breakdown phase change memory device 有权
标题翻译：受控击穿相变存储器件
公开(公告)号：US20060054996A1
公开(公告)日：2006-03-16
申请号：US10939237
申请日：2004-09-10
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L29/00
CPC分类号： H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/16
摘要： A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.
摘要翻译：相变记忆材料可以通过绝缘体沉积在孔中的电极上。可以通过使用胶层来改善记忆材料对绝缘体的粘附性。同时，可以在存储材料和电极之间的孔隙中形成击穿层。

47. 发明申请

US20060014379A1 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry 审中-公开
公开(公告)号：US20060014379A1
公开(公告)日：2006-01-19
申请号：US11218004
申请日：2005-09-01
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/485 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.

48. 发明申请

US20060002173A1 ACCESSING PHASE CHANGE MEMORIES 有权
标题翻译：访问相变记忆
公开(公告)号：US20060002173A1
公开(公告)日：2006-01-05
申请号：US10882860
申请日：2004-06-30
申请人： Ward Parkinson , Charles Dennison , Stephen Hudgens
发明人： Ward Parkinson , Charles Dennison , Stephen Hudgens
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/74 , G11C2213/76
摘要： A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.
摘要翻译：存储器可以包括相变存储器元件和串联连接的第一和第二选择器件。第二选择装置可以具有比第一选择装置更高的电阻和更大的阈值电压。在一个实施例中，第一选择装置可以具有基本上等于其保持电压的阈值电压。在一些实施例中，选择装置和存储元件可以由硫族化物制成。在一些实施例中，选择装置可以由不可编程的硫族化物制成。具有较高阈值电压的选择装置可能会对组合造成较低的泄漏，但也可能表现出增加的快速恢复。这种增加的快速恢复可以被具有较低阈值电压的选择装置抵消，导致在一些实施例中与低泄漏和高性能的组合。

49. 发明申请

US20050194620A1 Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby 有权
标题翻译：选择性地增加相变存储器单元中的下编程电极的顶电阻和由此获得的结构的方法
公开(公告)号：US20050194620A1
公开(公告)日：2005-09-08
申请号：US11087897
申请日：2005-03-23
申请人： Charles Dennison , Chien Chiang
发明人： Charles Dennison , Chien Chiang
IPC分类号： G11C16/02 , H01L45/00 , H01L27/148
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/52 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.
摘要翻译：本发明涉及一种形成相变存储器的方法。下电极设置在第一电介质膜中。下部电极包括上部和下部。上部延伸超过第一介电膜。上段电阻率高于下段。第二电介质膜设置在第一电介质膜的上方，并且在上表面具有与上部共面的上表面。

50. 发明申请

US20050020049A1 Method for an integrated circuit contact 失效
标题翻译：集成电路接触方法
公开(公告)号：US20050020049A1
公开(公告)日：2005-01-27
申请号：US10923242
申请日：2004-08-19
申请人： Charles Dennison , Trung Doan
发明人： Charles Dennison , Trung Doan
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路和器件的制造中形成垂直触点的工艺。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间可以重复上述过程。

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