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41. 发明授权

US06794900B2 Method and circuit for pre-emphasis equalization in high speed data communications 有权
标题翻译：高速数据通信中预加重均衡的方法和电路
公开(公告)号：US06794900B2
公开(公告)日：2004-09-21
申请号：US10205340
申请日：2002-07-24
申请人： Benjamim Tang , Richard C. Pierson
发明人： Benjamim Tang , Richard C. Pierson
IPC分类号： H03K19003
CPC分类号： H04L25/0286 , H04L25/0272 , H04L25/0288 , H04L25/03878
摘要： A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel.
摘要翻译：可以通过使用可编程脉冲整形来提供用于高速数据通信系统的预加重均衡的方法和电路。配置有预加重均衡电路的数据通信系统通过接收输入数据流并通过互连或其他传输信道输出数据流进行传输。数据可以通过配置有可编程预加重均衡的输出缓冲器，在输入级具有输入反相器，并在输出级输出反相器。在操作期间，一旦输入级的输入信号转变，例如从低电平到高电平状态，到输出级的输入信号被配置为全幅度以驱动传输通道。一旦输出级转变到一个完整的幅度，输出级的输入被配置成更接近中等幅度。从满量程到中等刻度的幅度变化量决定了输出缓冲器向传输通道提供的均衡量。

42. 发明授权

US08972216B2 Methods and apparatus for calibration of power converters 有权
标题翻译：电力转换器校准方法和装置
公开(公告)号：US08972216B2
公开(公告)日：2015-03-03
申请号：US13042914
申请日：2011-03-08
申请人： Benjamim Tang , Chun-Yen Lin , Rohan Samsi , Jinghong Guo , Tim M. Ng , Richard Pierson
发明人： Benjamim Tang , Chun-Yen Lin , Rohan Samsi , Jinghong Guo , Tim M. Ng , Richard Pierson
IPC分类号： G05F1/10 , H02M3/156 , H01L27/02 , B23K26/00 , G01R31/40 , H02M3/158 , H02M1/00
CPC分类号： H02M3/156 , B23K26/351 , G01R19/00 , G01R31/40 , G01R35/005 , H01L27/0211 , H02M3/1584 , H02M2001/0009
摘要： Methods and apparatus for a power regulator according to various aspects of the present invention may comprise a sensor adapted to generate a measurement of a voltage or a current. A memory may store a correction parameter that corresponds to the measurement, and a correction system may be adapted to adjust the measurement according to the correction parameter.
摘要翻译：根据本发明的各个方面的用于功率调节器的方法和装置可以包括适于产生电压或电流的测量的传感器。存储器可以存储对应于测量的校正参数，并且校正系统可以适于根据校正参数来调整测量。

43. 发明申请

US20140002932A1 Switching Regulator with Negative Current Limit Protection 有权
标题翻译：具有负极限保护的开关稳压器
公开(公告)号：US20140002932A1
公开(公告)日：2014-01-02
申请号：US13537907
申请日：2012-06-29
申请人： Benjamim Tang , Amir Babazadeh
发明人： Benjamim Tang , Amir Babazadeh
IPC分类号： H02H9/02
CPC分类号： H02M1/32 , H02M3/1584
摘要： A switching regulator includes a power stage for coupling to a load through an inductor. The power stage switches so that the power stage sources positive current to the load through a first transistor of the power stage during some periods and sinks negative current from the load through a second transistor of the power stage during other periods. The switching regulator further includes a protection circuit operable to force the second transistor into an off-state state responsive to the negative current flowing through the inductor exceeding a predetermined negative threshold.
摘要翻译：开关调节器包括用于通过电感器耦合到负载的功率级。功率级开关使得功率级在一段时间内通过功率级的第一晶体管向负载提供正电流，并且在其它时段期间通过功率级的第二晶体管从负载吸收负电流。开关调节器还包括保护电路，其可操作以响应于流过电感器的负电流超过预定的负阈值而迫使第二晶体管进入截止状态。

44. 发明授权

US08239579B2 PLL/DLL dual loop data synchronization 有权
标题翻译： PLL / DLL双循环数据同步
公开(公告)号：US08239579B2
公开(公告)日：2012-08-07
申请号：US12719450
申请日：2010-03-08
申请人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
发明人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： G06F15/16
CPC分类号： H04J3/047 , H04J3/062 , H04J3/0685 , H04L7/033
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，而不是本地引用。因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

45. 发明授权

US08193796B2 Multiphase power regulator with load adaptive phase control 有权
标题翻译：具有负载自适应相位控制功能的多相电源调节器
公开(公告)号：US08193796B2
公开(公告)日：2012-06-05
申请号：US12371835
申请日：2009-02-16
申请人： Benjamim Tang , Robert T. Carroll , Nicholas R. Steffen , Richard C. Pierson
发明人： Benjamim Tang , Robert T. Carroll , Nicholas R. Steffen , Richard C. Pierson
IPC分类号： G05F1/00
CPC分类号： H02M3/1584 , H02M2001/0012
摘要： Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency.A current sense circuit senses the current at each phase, a summing circuit coupled to the output of the current sense circuit provides the total current value of all the measured phases, a circuit coupled to the output of the summing circuit provides the time averaged total current value to a threshold detecting circuit that determines the number of phases at which the voltage regulator should be operating for maximum efficiency, and a circuit for comparing the number of phases that are operating to the number of phases at which the voltage regulator should be operating adjusts the number of active phases to the number of phases at which the voltage regulator should be operating for maximum efficiency.
摘要翻译：公开了一种功率调节器，用于向诸如微处理器的微电子器件提供精确调节的功率。通过优化功率调节器的功率效率来实现改进的功率调节。特别地，在多相系统中，活性相的数量增加或减少以达到最佳功率效率。当负载设备的负载电流需求通过调节活动相数量来最大化效率而改变时，多相电压调节器可以适应操作模式以最大化效率。确定调节器提供的电流总值和有效相的总数，将有效相的总数与最大效率提供电流总值所需的有效相数进行比较; 并且调整活动相的数量以提供最大效率的电流总值。电流感测电路感测每相的电流，耦合到电流检测电路的输出的求和电路提供所有测量相位的总电流值，耦合到求和电路的输出的电路提供时间平均总电流值到阈值检测电路，其确定电压调节器应该在最大效率下操作的相位数，以及用于将正在操作的相位数与用于调节电压的相位数进行比较的电路进行调整电压调节器应运行的相数达到最大效率的有效相数。

46. 发明授权

US07743168B2 PLL/DLL dual loop data synchronization 有权
标题翻译： PLL / DLL双循环数据同步
公开(公告)号：US07743168B2
公开(公告)日：2010-06-22
申请号：US12077002
申请日：2008-03-14
申请人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
发明人： Benjamim Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： G06F15/16
CPC分类号： H04J3/047 , H04J3/062 , H04J3/0685 , H04L7/033
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，而不是本地引用。因此，DLL调整来自PLL的频率，使其与期望的数据速率相匹配。每个环路可以针对抖动容限进行优化，其净效应产生合成的干净时钟（由于窄带宽滤波）和VCO噪声抑制（由于宽带宽滤波）。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

47. 发明授权

US06937685B2 Apparatus and method for counting high-speed early/late pulses from a high speed phase detector using a pulse accumulator 有权
标题翻译：用于使用脉冲累加器从高速相位检测器计数高速早/晚脉冲的装置和方法
公开(公告)号：US06937685B2
公开(公告)日：2005-08-30
申请号：US10008272
申请日：2001-11-13
申请人： Benjamim Tang
发明人： Benjamim Tang
IPC分类号： H03L7/081 , H03L7/087 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/14 , H04L7/033 , H03D3/24
CPC分类号： H03L7/089 , H03L7/081 , H03L7/0814 , H03L7/087 , H03L7/093 , H03L7/0996 , H03L7/14 , H04L7/0331 , H04L7/0337
摘要： The method and device according to the present invention provides a control system, method and apparatus for synchronizing a reference signal to high frequency data signals. Pulses are accumulated before reaching the integrator. Pulse accumulation is provided in a DLL clock and data recovery circuit. Pulses are accumulated using a ripple divider for rising transitions only. In another exemplary embodiment, pulses are accumulated using a ripple divider for both rising and falling transitions.
摘要翻译：根据本发明的方法和装置提供了一种用于使参考信号与高频数据信号同步的控制系统，方法和装置。脉冲在到达积分器之前累积。在DLL时钟和数据恢复电路中提供脉冲积累。使用纹波分配器对脉冲进行累积，仅用于上升转换。在另一示例性实施例中，使用用于上升和下降转换的波纹分配器累积脉冲。

48. 发明授权

US09285399B2 Switching regulator cycle-by-cycle current estimation 有权
标题翻译：开关稳压器逐周期电流估计
公开(公告)号：US09285399B2
公开(公告)日：2016-03-15
申请号：US13537827
申请日：2012-06-29
申请人： Amir Babazadeh , Benjamim Tang , Giuseppe Bernacchia
发明人： Amir Babazadeh , Benjamim Tang , Giuseppe Bernacchia
IPC分类号： G05F1/10 , G01R19/00 , H02M3/156 , H02M3/158 , H02M1/00
CPC分类号： G01R19/0092 , H02M3/156 , H02M3/1584 , H02M2001/0009 , H02M2003/1566
摘要： A switching regulator includes an output phase having a high-side transistor and a low-side transistor operable to switch on and off at different periods responsive to a pulse width modulation (PWM) signal applied to the output phase, each cycle of the PWM signal having an on-portion and an off-portion. The switching regulator further includes a current sense circuit operable to sense the current of the low-side transistor, an analog-to-digital converter operable to sample the sensed low-side transistor current during the off-portion for each PWM cycle and a current estimator operable to estimate a cycle average current for the present PWM cycle based on the low-side transistor current sampled during the off-portion for the immediately preceding PWM cycle and a pulse width estimate for the on-portion for the present PWM cycle.
摘要翻译：开关调节器包括具有高侧晶体管和低侧晶体管的输出相位，可操作以响应于施加到输出相位的脉冲宽度调制（PWM）信号在不同周期接通和关断PWM信号的每个周期具有一部分和一部分。开关调节器还包括可感测低侧晶体管的电流的电流检测电路，可操作以在每个PWM周期的截止部分期间对感测到的低侧晶体管电流进行采样的模数转换器和电流估计器，其可操作以基于在前一个PWM周期的截止部分期间采样的低侧晶体管电流以及用于当前PWM周期的导通部分的脉冲宽度估计来估计当前PWM周期的周期平均电流。

49. 发明授权

US09240721B2 Multiphase digital current mode controller with dynamic current allocation 有权
标题翻译：具有动态电流分配功能的多相数字电流模式控制器
公开(公告)号：US09240721B2
公开(公告)日：2016-01-19
申请号：US13547282
申请日：2012-07-12
申请人： Amir Babazadeh , Benjamim Tang , Giuseppe Bernacchia , Kenneth Ostrom
发明人： Amir Babazadeh , Benjamim Tang , Giuseppe Bernacchia , Kenneth Ostrom
IPC分类号： H02M3/158 , H02M1/00 , H02M3/156
CPC分类号： H02M3/1584 , H02M2001/0032 , H02M2003/1566 , Y02B70/16
摘要： A multiphase switching regulator includes a power stage with at least a first phase and a second phase for supplying power to a load through inductors coupling the phases to the load. The multiphase switching regulator is operated by switching the first phase at a higher switching frequency than the second phase via pulse width modulation (PWM) signals provided to the phases. A phase-specific target current is generated for each phase at the switching frequency for that phase based on the difference between an output voltage of the power stage and a reference voltage. The current in the inductors coupling the phases to the load is sensed, and a duty cycle of the PWM signal provided to each phase is adjusted based on the phase-specific target current and sensed inductor current for that phase.
摘要翻译：多相开关调节器包括具有至少第一相和第二相的功率级，用于通过将相耦合到负载的电感器向负载供电。通过经由提供给相的脉宽调制（PWM）信号，以比第二相更高的开关频率切换第一相来操作多相开关稳压器。基于功率级的输出电压和参考电压之间的差异，针对该相的开关频率的每相产生相位特定的目标电流。感测将相位耦合到负载的电感器中的电流，并且基于该相位的相位特定目标电流和检测到的电感器电流来调整提供给每个相位的PWM信号的占空比。

50. 发明授权

US08879217B2 Switching regulator with negative current limit protection 有权
标题翻译：开关稳压器带负极限流保护
公开(公告)号：US08879217B2
公开(公告)日：2014-11-04
申请号：US13537907
申请日：2012-06-29
申请人： Benjamim Tang , Amir Babazadeh
发明人： Benjamim Tang , Amir Babazadeh
IPC分类号： H02H3/22
CPC分类号： H02M1/32 , H02M3/1584
摘要： A switching regulator includes a power stage for coupling to a load through an inductor. The power stage switches so that the power stage sources positive current to the load through a first transistor of the power stage during some periods and sinks negative current from the load through a second transistor of the power stage during other periods. The switching regulator further includes a protection circuit operable to force the second transistor into an off-state state responsive to the negative current flowing through the inductor exceeding a predetermined negative threshold.
摘要翻译：开关调节器包括用于通过电感器耦合到负载的功率级。功率级开关使得功率级在一段时间内通过功率级的第一晶体管向负载提供正电流，并且在其它时段期间通过功率级的第二晶体管从负载吸收负电流。开关调节器还包括保护电路，其可操作以响应于流过电感器的负电流超过预定的负阈值而迫使第二晶体管进入截止状态。

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