专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07236410B2 Memory cell driver circuits 有权
标题翻译：存储单元驱动电路
公开(公告)号：US07236410B2
公开(公告)日：2007-06-26
申请号：US11169106
申请日：2005-06-27
申请人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
发明人： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
IPC分类号： G11C7/00 , G11C17/00 , G11C5/06
CPC分类号： G11C17/18
摘要： A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
摘要翻译：系统包括用于对存储器单元进行编程的上拉电路。上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍，并产生第二控制信号和共源共栅级。共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道电压和输出节点以提供单元编程信号。

42. 发明授权

US07075821B2 Apparatus and method for a one-phase write to a one-transistor memory cell array 失效
公开(公告)号：US07075821B2
公开(公告)日：2006-07-11
申请号：US10956407
申请日：2004-09-30
申请人： Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
发明人： Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C2211/4016
摘要： A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

43. 发明授权

US07057927B2 Floating-body dynamic random access memory with purge line 失效
标题翻译：具有清除线的浮动动态随机存取存储器
公开(公告)号：US07057927B2
公开(公告)日：2006-06-06
申请号：US11289621
申请日：2005-11-30
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.
摘要翻译：实施例涉及浮体动态随机存取存储器（FBDRAM）。在将数据写入FBDRAM单元之前，FBDRAM利用清除线来复位FBDRAM单元。

44. 发明授权

US07053449B2 Double gate transistor for low power circuits 有权
标题翻译：用于低功率电路的双栅极晶体管
公开(公告)号：US07053449B2
公开(公告)日：2006-05-30
申请号：US10254346
申请日：2002-09-24
申请人： Jaume A. Segura , Ali Keshavarzi , Vivek K. De
发明人： Jaume A. Segura , Ali Keshavarzi , Vivek K. De
IPC分类号： H01L29/76
CPC分类号： H01L29/7831
摘要： A double gate MOSFET having a control gate and a signal gate. The effective threshold voltage seen by the signal gate may be modified by charging the control gate. The effective threshold voltage may be increased in magnitude to reduce sub-threshold leakage current when the double gate MOSFET is inactive. When inactive, the control gate is maintained at a negative voltage for a double gate nMOSFET, and is maintained at a positive voltage for a double gate pMOSFET. When active, the control gate is charged to a voltage close to the threshold voltage, and then floated, so that a signal voltage applied to the signal gate may turn the double gate MOSFET ON during a signal voltage transition via the coupling capacitance between the signal and control gates.
摘要翻译：具有控制栅极和信号栅极的双栅极MOSFET。可以通过对控制栅极充电来修改由信号门看到的有效阈值电压。当双栅极MOSFET不活动时，有效阈值电压可以增加幅度以减小次阈值漏电流。当不活动时，对于双栅极nMOSFET，控制栅极保持在负电压，并且对于双栅极pMOSFET保持在正电压。当激活时，控制栅极被充电到接近阈值电压的电压，然后漂浮，使得施加到信号栅极的信号电压可以在信号电压转换期间通过信号之间的耦合电容将双栅极MOSFET导通和控制门。

45. 发明授权

US06952376B2 Method and apparatus to generate a reference value in a memory array 有权
公开(公告)号：US06952376B2
公开(公告)日：2005-10-04
申请号：US10740551
申请日：2003-12-22
申请人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
发明人： Dinesh Somasekhar , Yibin Ye , Muhammad M. Khellah , Fabrice Paillet , Stephen H. Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek K. De
IPC分类号： G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C7/02
CPC分类号： G11C11/4099 , G11C7/14 , G11C7/18 , G11C11/4097
摘要： An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.

46. 发明授权

US06794630B2 Method and apparatus for adjusting the threshold of a CMOS radiation-measuring circuit 失效
标题翻译：调整CMOS辐射测量电路阈值的方法和装置
公开(公告)号：US06794630B2
公开(公告)日：2004-09-21
申请号：US10024467
申请日：2001-12-17
申请人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Vivek K. De
IPC分类号： H01L3100
CPC分类号： G01T1/026 , H01L27/144
摘要： A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.
摘要翻译：辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。

47. 发明授权

US06545619B1 Switched current source 有权
标题翻译：开关电流源
公开(公告)号：US06545619B1
公开(公告)日：2003-04-08
申请号：US10040903
申请日：2001-12-28
申请人： Jaume A. Segura , Jose L. Rossello , Ali Keshavarzi , Siva G. Narendra , Vivek K. De
发明人： Jaume A. Segura , Jose L. Rossello , Ali Keshavarzi , Siva G. Narendra , Vivek K. De
IPC分类号： H03M166
CPC分类号： H01L27/088
摘要： A circuit includes a switched current source having a switching transistor coupled in series to a bias transistor. An isolation transistor is coupled in series to an output of the switched current source. The width of the switching transistor is greater than the width of the isolation transistor.
摘要翻译：电路包括具有与偏置晶体管串联耦合的开关晶体管的开关电流源。隔离晶体管与开关电流源的输出串联耦合。开关晶体管的宽度大于隔离晶体管的宽度。

48. 发明授权

US06484265B2 Software control of transistor body bias in controlling chip parameters 有权
标题翻译：控制芯片参数的晶体管体偏置的软件控制
公开(公告)号：US06484265B2
公开(公告)日：2002-11-19
申请号：US09224573
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： G06F132
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.
摘要翻译：在一些实施例中，本发明包括具有处理器和控制电路的系统。控制电路控制身体偏置信号的设置以控制处理器中提供的身体偏压，以至少部分地控制处理器的参数，其中控制电路根据处理器信号控制结果，从而执行软件。控制电路还可以控制电源电压信号和时钟信号的设置以控制参数。可以控制多个参数。参数的示例包括性能，功耗和温度。

49. 发明授权

US06272666B1 Transistor group mismatch detection and reduction 有权
标题翻译：晶体管组不匹配检测和还原
公开(公告)号：US06272666B1
公开(公告)日：2001-08-07
申请号：US09224574
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： G06F1750
CPC分类号： G01R31/2882 , G01R31/3016
摘要： In some embodiments, the invention includes a system having first and second domains. The system includes a first performance detection circuitry including some transistors of the first domain to provide a first performance rating signal indicative of transistor switching rates of the first domain. The system includes second performance detection circuitry including some transistors of the second domain to provide a second performance rating signal indicative of transistor switching rates the second domain. The system further includes control circuitry to receive the first and second performance rating signals and control a setting for a body bias signal for the first domain and control a setting for a body bias signal for the second domain responsive to the performance rating signals. In some embodiments, the control circuitry also provides supply voltage signals and clock signals responsive to the performance signals. The first and second domains may have clock signals with the same frequency and the bias values are set such that the transistors of the first and second domains can switch properly while the first and second domains have the clock signals and wherein one of the first and second domains operates at less than optimal performance.
摘要翻译：在一些实施例中，本发明包括具有第一和第二域的系统。该系统包括第一性能检测电路，其包括第一域的一些晶体管，以提供指示第一域的晶体管切换速率的第一性能评估信号。该系统包括第二性能检测电路，其包括第二域的一些晶体管，以提供指示第二域的晶体管切换速率的第二性能评估信号。该系统还包括控制电路，用于接收第一和第二性能评定信号并且控制针对第一域的体偏置信号的设置，并且响应于性能等级信号来控制针对第二域的体偏置信号的设置。在一些实施例中，控制电路还响应于性能信号提供电源电压信号和时钟信号。第一和第二域可以具有相同频率的时钟信号，并且偏置值被设置为使得第一和第二域的晶体管可以正确地切换，而第一和第二域具有时钟信号，并且其中第一和第二域中的一个域以不到最佳性能运行。

50. 发明授权

US08138042B2 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US08138042B2
公开(公告)日：2012-03-20
申请号：US12967238
申请日：2010-12-14
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式