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41. 发明申请

US20140273488A1 PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING 审中-公开
公开(公告)号：US20140273488A1
公开(公告)日：2014-09-18
申请号：US14246978
申请日：2014-04-07
申请人： APPLIED MATERIALS, INC.
发明人： Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC分类号： H01L21/67 , H01L21/3065
CPC分类号： H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
摘要： Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

42. 发明申请

US20140262038A1 PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING 有权
公开(公告)号：US20140262038A1
公开(公告)日：2014-09-18
申请号：US14246915
申请日：2014-04-07
申请人： APPLIED MATERIALS, INC.
发明人： Anchuan Wang , Xinglong Chen , Zihui Li , Hiroshi Hamana , Zhijun Chen , Ching-Mei Hsu , Jiayin Huang , Nitin K. Ingle , Dmitry Lubomirsky , Shankar Venkataraman , Randhir Thakur
IPC分类号： H01L21/67
CPC分类号： H01L21/324 , C23C16/4405 , H01J37/32357 , H01J37/32862 , H01L21/02041 , H01L21/02057 , H01L21/0206 , H01L21/263 , H01L21/2686 , H01L21/30604 , H01L21/3065 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L21/67069 , H01L21/67075 , H01L21/6708 , H01L21/67109 , H01L21/67115 , H01L21/67184 , H01L21/6719 , H01L21/67196 , H01L21/67201 , H01L21/67207 , H01L21/67248 , H01L21/67253 , H01L21/67288 , H01L21/67703 , H01L21/67739 , H01L21/67742 , H01L21/6831
摘要： Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

43. 发明申请

US20140227881A1 SEMICONDUCTOR PROCESSING SYSTEMS HAVING MULTIPLE PLASMA CONFIGURATIONS 审中-公开
标题翻译：具有多个等离子体配置的半导体处理系统
公开(公告)号：US20140227881A1
公开(公告)日：2014-08-14
申请号：US13791074
申请日：2013-03-08
申请人： Applied Materials, Inc.
发明人： Dmitry Lubomirsky , Xinglong Chen , Shankar Venkataraman
IPC分类号： H01L21/67 , H01L21/3065
CPC分类号： H01J37/32357 , C23C16/45565 , C23C16/505 , C23C16/54 , H01J37/32422 , H01J37/32449 , H01J37/32899 , H01L21/32136 , H01L21/67069
摘要： An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.
摘要翻译：示例性系统可以包括被配置成在腔室的处理区域中容纳半导体衬底的腔室。该系统可以包括第一远程等离子体单元，该第一远程等离子体单元与腔室的第一通路流体耦合并且被配置为通过第一通路将第一前体输送到腔室中。系统还可以包括第二远程等离子体单元，该第二远程等离子体单元与腔室的第二通路流体耦合并且被配置为通过第二通路将第二前体输送到腔室中。第一和第二通路可以与腔室的混合区域流体耦合，腔室的混合区域与腔室的处理区域分开并与腔室的处理区域流体耦合。混合区域可以被配置为允许第一和第二前体在室的处理区域外部彼此相互作用。

44. 发明申请

US20130252440A1 PRETREATMENT AND IMPROVED DIELECTRIC COVERAGE 审中-公开
标题翻译：预处理和改进的电介质覆盖
公开(公告)号：US20130252440A1
公开(公告)日：2013-09-26
申请号：US13623792
申请日：2012-09-20
申请人： APPLIED MATERIALS, INC.
发明人： Lei Luo , Shankar Venkataraman , Manuel A. Hernandez , Kedar Sapre , Zhong Qiang Hua
IPC分类号： H01L21/02
CPC分类号： H01L21/0226 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02315 , H01L21/02362 , H01L21/76831 , H01L21/76898
摘要： Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance.
摘要翻译：描述了在图案化衬底上共形沉积氧化硅层的方法。图案化的衬底被等离子体处理，使得随后沉积的氧化硅层可以均匀地沉积在深闭合的沟槽的壁上。该技术对于需要特别深的沟槽的贯通衬底通孔（TSV）特别有用。沟槽可以在底部和深处封闭，以便通过稍后去除背面衬底的一部分（靠近沟槽的封闭端）来实现贯穿衬底通孔（TSV）。在本发明的实施方案中，靠近沟槽底部的侧壁上的共形氧化硅层厚度大于或接近沟槽顶部的共形氧化硅层厚度的约70％。氧化硅层的改进的均匀性使得随后沉积的导电插头更厚并且提供更少的电阻。

45. 发明公开

US20240363337A1 METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS 审中-公开
公开(公告)号：US20240363337A1
公开(公告)日：2024-10-31
申请号：US18139699
申请日：2023-04-26
申请人： Applied Materials, Inc.
发明人： Muthukumar Kaliappan , Bo Xie , Shanshan Yao , Li-Qun Xia , Michael Haverty , Rui Lu , Xiaobo Li , Chi-I Lang , Shankar Venkataraman
IPC分类号： H01L21/02 , C23C16/32 , C23C16/455 , C23C16/56
CPC分类号： H01L21/02167 , C23C16/325 , C23C16/45542 , C23C16/45553 , C23C16/45565 , C23C16/56 , H01L21/02211 , H01L21/02274
摘要： Semiconductor processing methods are described for forming low-κ dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.

46. 发明授权

US10550472B2 Flow control features of CVD chambers 有权
公开(公告)号：US10550472B2
公开(公告)日：2020-02-04
申请号：US14481774
申请日：2014-09-09
申请人： Applied Materials, Inc.
发明人： Kien N. Chuc , Qiwei Liang , Hanh D. Nguyen , Xinglong Chen , Matthew Miller , Soonam Park , Toan Q. Tran , Adib Khan , Jang-Gyoo Yang , Dmitry Lubomirsky , Shankar Venkataraman
IPC分类号： C23C16/455 , H01J37/32 , C23C16/452
摘要： Apparatus and methods for gas distribution assemblies are provided. In one aspect, a gas distribution assembly is provided comprising an annular body comprising an annular ring having an inner annular wall, an outer wall, an upper surface, and a bottom surface, an upper recess formed into the upper surface, and a seat formed into the inner annular wall, an upper plate positioned in the upper recess, comprising a disk-shaped body having a plurality of first apertures formed therethrough, and a bottom plate positioned on the seat, comprising a disk-shaped body having a plurality of second apertures formed therethrough which align with the first apertures, and a plurality of third apertures formed between the second apertures and through the bottom plate, the bottom plate sealingly coupled to the upper plate to fluidly isolate the plurality of first and second apertures from the plurality of third apertures.

47. 发明申请

US20170229326A1 LOW TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS 审中-公开
公开(公告)号：US20170229326A1
公开(公告)日：2017-08-10
申请号：US15581497
申请日：2017-04-28
申请人： Applied Materials, Inc.
发明人： Toan Q. Tran , Zilu Weng , Dmitry Lubomirsky , Satoru Kobayashi , Tae Seung Cho , Soonam Park , Son M. Phi , Shankar Venkataraman
IPC分类号： H01L21/67 , H01L21/683
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/67103 , H01L21/67248 , H01L21/6831 , H01L21/68757 , H01L21/68785 , H01L21/68792
摘要： A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

48. 发明授权

US09496167B2 Integrated bit-line airgap formation and gate stack post clean 有权
标题翻译：集成位线气隙形成和门堆叠柱清洁
公开(公告)号：US09496167B2
公开(公告)日：2016-11-15
申请号：US14448059
申请日：2014-07-31
申请人： Applied Materials, Inc.
发明人： Vinod R. Purayath , Randhir Thakur , Shankar Venkataraman , Nitin K. Ingle
IPC分类号： H01L21/764 , H01L27/115 , H01L21/311 , H01L29/06 , H01L21/28 , H01L29/66 , H01L21/02
CPC分类号： H01L21/764 , H01J37/32357 , H01L21/02071 , H01L21/28273 , H01L21/28282 , H01L21/31116 , H01L21/67069 , H01L21/67103 , H01L21/68764 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/66833 , H01L29/7887
摘要： Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.
摘要翻译：描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

49. 发明申请

US20160225652A1 LOW TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS 审中-公开
标题翻译：等离子体加工系统的低温冲击
公开(公告)号：US20160225652A1
公开(公告)日：2016-08-04
申请号：US14612857
申请日：2015-02-03
申请人： Applied Materials, Inc.
发明人： Toan Q. Tran , Zilu Weng , Dmitry Lubomirsky , Satoru Kobayashi , Tae Seung Cho , Soonam Park , Son M. Phi , Shankar Venkataraman
IPC分类号： H01L21/683 , H01L21/3065 , H01L21/67
CPC分类号： H01L21/67069 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/67103 , H01L21/67248 , H01L21/6831 , H01L21/68757 , H01L21/68785 , H01L21/68792
摘要： A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.
摘要翻译：晶片卡盘组件包括圆盘，轴和基座。圆盘包括限定冰球顶表面的电绝缘材料; 多个电极嵌入电绝缘材料内。该圆盘还包括内部圆盘元件，其形成用于热交换流体的一个或多个通道，内部圆盘元件与电绝缘材料热连通，以及设置在靠近内部圆锥元件的导电板。所述轴包括与所述板电耦合的导电轴壳体，以及包括用于所述电极的电连接器的多个连接器。基座包括与轴壳体电耦合的导电基座壳体，以及设置在基座壳体内的电绝缘接线块，多个连接器穿过接线端子。

50. 发明申请

US20160225651A1 HIGH TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS 有权
标题翻译：用于等离子体加工系统的高温冲击
公开(公告)号：US20160225651A1
公开(公告)日：2016-08-04
申请号：US14612472
申请日：2015-02-03
申请人： Applied Materials, Inc.
发明人： Toan Q. Tran , Sultan Malik , Dmitry Lubomirsky , Shambhu N. Roy , Satoru Kobayashi , Tae Seung Cho , Soonam Park , Shankar Venkataraman
IPC分类号： H01L21/683 , H01L21/67 , H01L21/3065
CPC分类号： H01L21/6833 , H01L21/3065 , H01L21/67103
摘要： A wafer chuck assembly includes a puck, a shaft and a base. An insulating material defines a top surface of the puck, a heater element is embedded within the insulating material, and a conductive plate lies beneath the insulating material. The shaft includes a housing coupled with the plate, and electrical connectors for the heater elements and the electrodes. A conductive base housing couples with the shaft housing, and the connectors pass through a terminal block within the base housing. A method of plasma processing includes loading a workpiece onto a chuck having an insulating top surface, providing a DC voltage differential across two electrodes within the top surface, heating the chuck by passing current through heater elements, providing process gases in a chamber surrounding the chuck, and providing an RF voltage between a conductive plate beneath the chuck, and one or more walls of the chamber.
摘要翻译：晶片卡盘组件包括圆盘，轴和基座。绝缘材料限定了圆盘的顶表面，加热元件嵌入绝缘材料内，导电板位于绝缘材料的下方。轴包括与板连接的壳体，以及用于加热器元件和电极的电连接器。导电基座壳体与轴壳体耦合，并且连接器穿过基座壳体内的端子块。等离子体处理的方法包括将工件加载到具有绝缘顶表面的卡盘上，在顶表面内的两个电极之间提供直流电压差，通过使电流通过加热器元件来加热卡盘，在围绕卡盘的腔室中提供工艺气体并且在卡盘下方的导电板与腔室的一个或多个壁之间提供RF电压。

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