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41. 发明授权

US08759894B1 System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
标题翻译：用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法
公开(公告)号：US08759894B1
公开(公告)日：2014-06-24
申请号：US11189765
申请日：2005-07-27
申请人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
发明人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
IPC分类号： H01L29/78
CPC分类号： H01L27/11524 , H01L21/28273 , H01L29/66825 , H01L29/66833
摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
摘要翻译：提供了包括基板的存储器件。第一电介质层形成在衬底上。在衬底和第一介电层的一部分中形成隔离沟槽。在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。在所述至少两个电荷存储元件上形成第二电介质层。控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度所述至少两个电荷存储元件和所述控制栅极层。

42. 发明授权

US08409994B2 Gate trim process using either wet etch or dry etch approach to target CD for selected transistors 有权
标题翻译：使用湿蚀刻或干法蚀刻方法对所选晶体管靶CD进行栅极修整处理
公开(公告)号：US08409994B2
公开(公告)日：2013-04-02
申请号：US13278343
申请日：2011-10-21
申请人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
发明人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132 , H01L21/823456
摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
摘要翻译：公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

43. 发明申请

US20120139023A1 METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION 审中-公开
标题翻译：用于存储源/漏区的NAND存储器的方法和装置
公开(公告)号：US20120139023A1
公开(公告)日：2012-06-07
申请号：US12960411
申请日：2010-12-03
申请人： Chun CHEN , Angela T. Hui , Fei Wang
发明人： Chun CHEN , Angela T. Hui , Fei Wang
IPC分类号： H01L29/78 , H01L21/04 , G06F17/50
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/1157 , H01L29/792
摘要： A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line.
摘要翻译：提供了一种用于闪速存储器的方法和装置。 NAND闪存阵列包括单元体，第一选择栅极和第一边缘线。电池体包括在第一选择栅极和第一边缘字线之间的凹入的掺杂源极/漏极区域。

44. 发明授权

US08114736B2 Integrated circuit system with memory system 有权
标题翻译：具有存储系统的集成电路系统
公开(公告)号：US08114736B2
公开(公告)日：2012-02-14
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

45. 发明授权

US07977797B2 Integrated circuit with contact region and multiple etch stop insulation layer 有权
标题翻译：具有接触区域和多个蚀刻停止绝缘层的集成电路
公开(公告)号：US07977797B2
公开(公告)日：2011-07-12
申请号：US12539480
申请日：2009-08-11
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L23/522
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是一种半导体接触形成系统和方法。接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。导电材料（例如，钨）沉积在接触区域中。

46. 发明申请

US20080153298A1 MEMORY DEVICE ETCH METHODS 有权
标题翻译：存储器件蚀刻方法
公开(公告)号：US20080153298A1
公开(公告)日：2008-06-26
申请号：US11616085
申请日：2006-12-26
申请人： Angela T. Hui , Jihwan Choi
发明人： Angela T. Hui , Jihwan Choi
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136 , H01L21/32137 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.
摘要翻译：一种制造存储器件的方法在衬底上形成第一介电层，在第一介电层之上形成电荷存储层，在电荷存储层上形成第二介电层，并在第二介电层上形成控制栅极层。该方法还在控制栅极层上形成硬掩模层，在硬掩模层之上形成底部抗反射涂层（BARC）层，并提供包括四氟甲烷（CF 4 N）和三氟甲烷（CHF 3 N 3），以至少蚀刻控制栅极层。

47. 发明申请

US20080142873A1 INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE 有权
标题翻译：具有金属和半导体门的集成电路系统
公开(公告)号：US20080142873A1
公开(公告)日：2008-06-19
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

48. 发明授权

US07265014B1 Avoiding field oxide gouging in shallow trench isolation (STI) regions 有权
标题翻译：在浅沟槽隔离（STI）区域避免场氧化物气刨
公开(公告)号：US07265014B1
公开(公告)日：2007-09-04
申请号：US10799413
申请日：2004-03-12
申请人： Angela T. Hui , Jusuke Ogura , Yider Wu
发明人： Angela T. Hui , Jusuke Ogura , Yider Wu
IPC分类号： H01L21/764 , H01L29/00
CPC分类号： H01L21/76224
摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.
摘要翻译：一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。可以在STI区域中蚀刻沟槽并填充绝缘材料。抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。可以将保护盖回蚀以暴露ARC层。然而，保护盖仍然覆盖并保护绝缘材料。通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

49. 发明授权

US07238571B1 Non-volatile memory device with increased reliability 有权
标题翻译：非易失性存储器件具有更高的可靠性
公开(公告)号：US07238571B1
公开(公告)日：2007-07-03
申请号：US11063560
申请日：2005-02-24
申请人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
发明人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
摘要翻译：存储器件可以包括多个存储器单元，形成在存储器单元上的第一层间电介质和形成在层间电介质上的至少一个金属层。介电层可以形成在金属层的上方。电介质层可以表示在存储器件的上表面处或附近形成的覆盖层，并且可以在相对低的温度下沉积。

50. 发明授权

US06803267B1 Silicon containing material for patterning polymeric memory element 有权
标题翻译：含硅材料用于图案化聚合物记忆元件
公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译：本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料上电极通过有机半导体材料和被动材料到下电极。有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

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