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41. 发明授权

US08390330B2 Base cell for implementing an engineering change order (ECO) 有权
标题翻译：用于实施工程变更单（ECO）的基本单元
公开(公告)号：US08390330B2
公开(公告)日：2013-03-05
申请号：US13096297
申请日：2011-04-28
申请人： Luca Ciccarelli , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Valentina Nardone
发明人： Luca Ciccarelli , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Valentina Nardone
IPC分类号： H01L25/00 , H01L27/118
CPC分类号： G06F17/5068
摘要： A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.
摘要翻译：电路基座用于实现在半导体衬底上获得的工程改变顺序（ECO）。基体单元可以包括具有第一有源区的PMOS晶体管，该第一有源区在植入在衬底上设置的N阱中的第一扩散P +层中，以及NMOS晶体管，其具有在第二扩散N +层中所获得的第二有源区，该衬底以与第一扩散P +层电绝缘的方式。电池的特征在于有源区域和扩散层相对于参考轴线在其间对准，并且它们在与轴线正交的方向上对称延伸。第一和第二宽度可以分别与有源区域和扩散层相关联。第一和第二宽度可以大于单元的宽度，其等于标准最小单元的间距。

42. 发明申请

US20130001547A1 METHOD FOR VERIFYING THE ALIGNMENT BETWEEN INTEGRATED ELECTRONIC DEVICES 有权
标题翻译：用于验证集成电子设备之间的对准的方法
公开(公告)号：US20130001547A1
公开(公告)日：2013-01-03
申请号：US13295600
申请日：2011-11-14
申请人： Roberto Canegallo , Mauro Scandiuzzo , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Guerrieri
发明人： Roberto Canegallo , Mauro Scandiuzzo , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Guerrieri
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L23/48 , H01L22/34 , H01L25/0657 , H01L25/50 , H01L2225/06531 , H01L2225/06565 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A method includes communicatively coupling first and second integrated electronic devices together through a plurality of reference capacitors, transmitting a plurality of transmission reference signals on transmission reference electrodes of the plurality of reference capacitors, receiving coupling signals on reception reference electrodes of the plurality of reference capacitors, amplifying said coupling signals, generating a plurality of reception reference signals, generating a plurality of reception control signals as a function of the plurality of reception reference signals, and detecting a possible misalignment between said first and second integrated electronic devices based on the plurality of reception control signals.
摘要翻译：一种方法包括通过多个参考电容器将第一和第二集成电子设备通信地耦合在一起，在多个参考电容器的发射参考电极上传输多个发射参考信号，在多个参考电容器的接收参考电极上接收耦合信号放大所述耦合信号，产生多个接收参考信号，产生作为多个接收参考信号的函数的多个接收控制信号，以及基于多个接收参考信号检测所述第一和第二集成电子设备之间可能的未对准接收控制信号。

43. 发明授权

US08238502B2 Communication system between a first and a second synchronous device that are uncorrelated in time 有权
标题翻译：第一和第二同步设备之间的通信系统在时间上不相关
公开(公告)号：US08238502B2
公开(公告)日：2012-08-07
申请号：US12345459
申请日：2008-12-29
申请人： Luca Magagni , Luca Ciccarelli , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Magagni , Luca Ciccarelli , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H04L7/00
CPC分类号： H04L7/10 , H04L7/0037
摘要： A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.
摘要翻译：通信系统包括第一和第二独立计时装置，对于每个装置，包括对应于芯片间通信信道以交叉方式相互连接的发射机和接收机。所述通信系统还包括同步器，其又包括至少第一和第二同步块，其具有连接到接收器的相应输入端子和连接到发射器的相应输出端子，并且至少包括：产生可编程测试的测试模式发生器模式信号; 模式检测器，用于检查存储和接收的测试模式信号之间的匹配，从而在该检查的肯定结果的情况下锁定同步块的相应时钟相位; 以及能够改变时钟相位直到同步块的同步状态被验证的延迟块，该同步条件对应于存储和接收的测试模式信号之间的匹配。

44. 发明申请

US20120075920A1 MEMORY BASE CELL AND MEMORY BANK 有权
标题翻译：存储基础单元和存储器银行
公开(公告)号：US20120075920A1
公开(公告)日：2012-03-29
申请号：US13097502
申请日：2011-04-29
申请人： Valentina NARDONE , Stefano Pucillo , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Luca Perugini
发明人： Valentina NARDONE , Stefano Pucillo , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Luca Perugini
IPC分类号： G11C11/00 , H01F41/00
CPC分类号： G11C11/412 , Y10T29/49069
摘要： A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.
摘要翻译：存储器基座存储从“多数相同和复制的基本元件”构成的规则紧凑的结构实现的信息位，在“海上大门”模型中，其中该结构的基本元件是能够被配置的单元相对于所使用的特定技术具有最小宽度。这种单元包括双稳态元件，其输入节点可操作地连接到存储器基本单元的写入数据线，以及可操作地连接到存储器基本单元的读取数据线的输出节点。双稳态元件还具有在双稳态元件的输入节点和输出节点之间相对于彼此布置成反馈配置的第一反相器和第二反相器。

45. 发明申请

US20120001655A1 BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) 有权
标题翻译：实施工程变更订单（ECO）的基础单元
公开(公告)号：US20120001655A1
公开(公告)日：2012-01-05
申请号：US13096297
申请日：2011-04-28
申请人： Luca CICCARELLI , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Valentina Nardone
发明人： Luca CICCARELLI , Roberto Canegallo , Claudio Mucci , Massimiliano Innocenti , Valentina Nardone
IPC分类号： H03K19/0948 , H01L27/088 , H01L21/8234 , H01L27/092
CPC分类号： G06F17/5068
摘要： A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.
摘要翻译：电路基座用于实现在半导体衬底上获得的工程改变顺序（ECO）。基体单元可以包括具有第一有源区的PMOS晶体管，该第一有源区在植入在衬底上提供的N阱中的第一扩散P +层中，以及NMOS晶体管，其具有在第二扩散N +层中所获得的第二有源区，该衬底以与第一扩散P +层电绝缘的方式。电池的特征在于有源区域和扩散层相对于参考轴线在其间对准，并且它们在与轴线正交的方向上对称延伸。第一和第二宽度可以分别与有源区域和扩散层相关联。第一和第二宽度可以大于单元的宽度，其等于标准最小单元的间距。

46. 发明授权

US07772888B2 Communication system for connecting synchronous devices that are uncorrelated in time 有权
标题翻译：用于连接不及时相关的同步设备的通信系统
公开(公告)号：US07772888B2
公开(公告)日：2010-08-10
申请号：US12345479
申请日：2008-12-29
申请人： Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Ciccarelli , Luca Magagni , Alberto Fazzi , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： G06F13/4077 , H04L25/0266 , H04L25/028
摘要： A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.
摘要翻译：一种用于在定时非相关同步装置之间的连接的通信系统，包括至少一个发射机和一个接收机之间的连接，插入在第一和第二电压基准之间并且通过与相应的发射和接收终端对应的传输信道彼此连接。有利地，接收机包括至少一个异步输入级，适于在接收终端上接收与同步接收终端上的时钟信号同步的适于发送该数据的同步输出级的数据。一种方法通过用于在独立计时的设备之间的连接的通信系统中的电容性通道将来自发射器的数据传送到由接收器互连的接收器。

47. 发明授权

US07463067B2 Switch block for FPGA architectures 有权
标题翻译： FPGA架构的开关块
公开(公告)号：US07463067B2
公开(公告)日：2008-12-09
申请号：US11537781
申请日：2006-10-02
申请人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
发明人： Luca Ciccarelli , Andrea Lodi , Roberto Giansante , Luca Magagni , Roberto Canegallo , Roberto Guerrieri
IPC分类号： H03K19/094
CPC分类号： H03K19/177
摘要： A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.
摘要翻译：用于结合硬件和软件技术的FPGA架构的开关块，以减少主动和待机泄漏功率。

48. 发明授权

US07225319B2 Digital architecture for reconfigurable computing in digital signal processing 有权
标题翻译：用于数字信号处理中的可重构计算的数字架构
公开(公告)号：US07225319B2
公开(公告)日：2007-05-29
申请号：US10770122
申请日：2004-02-02
申请人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
发明人： Fabio Campi , Mario Toma , Andrea Lodi , Andrea Cappelli , Roberto Canegallo , Roberto Guerrieri
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3885 , G06F9/3877 , G06F9/3897 , G06F15/7867
摘要： A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.
摘要翻译：数字嵌入式架构包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，并且包括：处理器，被构造为通过通用硬连线计算逻辑实现非常长的指令字精炼模式，以及额外的数据描述信道包括基于由专用控制单元控制的基于可配置查找表的基于流水线阵列的可重配置功能单元，从而缓解了关键内核算法的详细描述。

49. 发明授权

US06448842B2 High-efficiency bidirectional voltage boosting device 有权
标题翻译：高效双向升压装置
公开(公告)号：US06448842B2
公开(公告)日：2002-09-10
申请号：US09788623
申请日：2001-02-13
申请人： Mauro Zanuccoli , Roberto Canegallo , Davide Dozza
发明人： Mauro Zanuccoli , Roberto Canegallo , Davide Dozza
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together. Each voltage boosting stage is connected to the adjacent stages via a first transfer node and a second transfer node and includes a storage capacitor connected at a terminal thereof to the second transfer node and receiving on the other terminal a first phase signal switching between a first value and a second value; a switch element including an NMOS transistor connected between the first transfer node and the second transfer node; a voltage boosting capacitor connected at a terminal thereof to the control terminal of the switch element and receiving on the other terminal a second phase signal; a first precharge circuit connected between the first transfer node and the control terminal of the switch element so as to control charge transfer from the first transfer node to the second transfer node when activated by a first activation signal; and a second precharge circuit connected between the second transfer node and the control terminal of the switch element so as to control charge transfer from the second transfer node to the first transfer node when activated by a second activation signal. The first activation signal and second activation signal are never active simultaneously.
摘要翻译：一种升压装置，具有由多个级联在一起的升压级形成的电荷泵电路。每个升压级经由第一传输节点和第二传输节点连接到相邻级，并且包括在其端子处连接到第二传输节点的存储电容器，并且在另一终端上接收第一相位信号，该第一相位信号在第一值和第二个值; 开关元件，包括连接在第一传输节点和第二传输节点之间的NMOS晶体管; 在其端子处连接到开关元件的控制端子并在另一端子上接收第二相位信号的升压电容器; 连接在第一传送节点和开关元件的控制端之间的第一预充电电路，以便当由第一激活信号激活时，控制从第一传输节点到第二传输节点的电荷传输; 以及第二预充电电路，连接在第二传输节点和开关元件的控制端之间，以便当由第二激活信号激活时，控制从第二传输节点到第一传输节点的电荷传输。第一激活信号和第二激活信号从不同时激活。

50. 发明授权

US08773162B2 Communication cell for an integrated circuit, chip comprising said communication cell, electronic system including the chip, and test apparatus 有权
标题翻译：用于集成电路的通信单元，包括所述通信单元的芯片，包括芯片的电子系统和测试装置
公开(公告)号：US08773162B2
公开(公告)日：2014-07-08
申请号：US12980832
申请日：2010-12-29
申请人： Roberto Canegallo , Roberto Cardu , Mauro Scandiuzzo , Salvatore Valerio Cani , Luca Perugini
发明人： Roberto Canegallo , Roberto Cardu , Mauro Scandiuzzo , Salvatore Valerio Cani , Luca Perugini
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： H03K19/0175 , H01L25/0657 , H01L2224/32145 , H01L2924/01021 , H01L2924/13091
摘要： An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the integrated circuit and the output terminal of the signal-selection means, configured for receiving the output signal and providing the output signal to the integrated circuit.
摘要翻译：一种通信单元的实施例，用于实现与集成电路不同的集成电路和电子单元之间的数据通信，包括接触焊盘单元，其被配置为在所述通信单元的第一操作状态下电容耦合到用于接收的电子单元来自所述电子单元的输入信号，并用于在所述通信单元的第二操作状态下欧姆耦合到用于接收输入信号的电子单元; 耦合在所述接触焊盘单元和所述集成电路之间的接收器装置，包括信号放大装置，被配置为接收输入信号并产生与输入信号相关的中间信号; 信号选择装置，在第一操作状态期间接收中间信号，输入信号，并提供作为中间信号的输出信号，以及在第二操作条件期间输入输入信号; 以及输入级，可连接在所述集成电路和所述信号选择装置的输出端之间，用于接收所述输出信号并将所述输出信号提供给所述集成电路。

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