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41. 发明授权

US6085303A Seralized race-free virtual barrier network 失效
标题翻译：无线化的无竞争虚拟屏障网络
公开(公告)号：US6085303A
公开(公告)日：2000-07-04
申请号：US972010
申请日：1997-11-17
申请人： Greg Thorson , Randal S. Passint , Steven L. Scott
发明人： Greg Thorson , Randal S. Passint , Steven L. Scott
IPC分类号： G06F9/46 , G06F15/16
CPC分类号： G06F9/52
摘要： Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts. The present synchronization mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes. The present barrier/eureka mechanism also supports zero to N processor entities at each router node ("leaves" on the barrier tree), and provides a barrier sequence counter for each barrier context in order to resolve potential race conflicts that might otherwise arise.
摘要翻译：改进的方法和装置，用于在大规模并行处理系统中促进障碍和尤里卡同步。当前的屏障/尤里卡同步机制提供了一种可分割的，低延迟的，立即可重用的鲁棒机制，其可以在物理数据通信网络上操作，并且可以用于警告所有PE中的所有处理器实体（PE）在该分区已经到达其个别程序代码中的指定障碍点，或者当该分区中的任何一个PE在其各个程序代码中已经达到指定的尤里卡点时，或者当满足屏障或尤里卡要求时，哪个曾经来过多个重叠的同步分区可以通过使用多个并行同步上下文同时获得。本同步机制可以在专用屏障网络上实现，或者叠加在用于数据交换，操作系统功能和其他目的的物理数据通信网络上操作的虚拟屏障/尤里卡网络。当前的屏障/尤里卡机制还支持每个路由器节点处的零到N个处理器实体（“阻挡树”上的“离开”），并且为每个屏障上下文提供屏障序列计数器，以便解决否则可能出现的潜在的竞争冲突。

42. 发明授权

US08792512B2 Reliable message transport network 有权
标题翻译：可靠的消息传输网络
公开(公告)号：US08792512B2
公开(公告)日：2014-07-29
申请号：US11759748
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/188 , H04L2001/0096
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。所述发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，以维护包括所发送的分组的所述发送方中的消息缓冲器条目，以跟踪已经接收到发送分组的来自所述接收机的确认; 以保持指示从消息数据发送起的时间的定时器，并且重新发送在定时器达到超时状态时未被确认的分组。接收处理器节点可操作以向接收到分组的发送方发送确认，以使用接收到的消息表来跟踪分组，以跟踪已经接收了包含消息的一部分的分组以及消息中的所有分组是否已被接收，并且一旦接收到消息中的所有分组以重新组合接收到的消息，则处理分组。

43. 发明授权

US08184626B2 High-radix interprocessor communications system and method 有权
标题翻译：高基处理器通信系统及方法
公开(公告)号：US08184626B2
公开(公告)日：2012-05-22
申请号：US12352443
申请日：2009-01-12
申请人： Steven L. Scott , Dennis C. Abts , William J. Dally
发明人： Steven L. Scott , Dennis C. Abts , William J. Dally
IPC分类号： H04L12/50
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n x p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.
摘要翻译：具有多个处理器节点，多个第一路由器和多个第二路由器的高基数处理器通信系统和方法。每个第一路由器连接到处理器节点和两个或更多个第二路由器。每个第一路由器包括输入端口，输出端口，行总线，列通道和以n×p矩阵排列的多个子开关。每行总线从多个输入端口之一接收数据，并将数据分配给多个子开关中的两个或多个。每列将数据从一个或多个子交换分配到一个或多个输出端口。每行行总线包括路由选择器，其中路由选择器包括路由选择表，该路由表选择每个分组的输出端口，并且通过一条行总线将分组路由到所选输出端口。

44. 发明授权

US08095759B2 Error management firewall in a multiprocessor computer 有权
标题翻译：多处理器计算机中的错误管理防火墙
公开(公告)号：US08095759B2
公开(公告)日：2012-01-10
申请号：US12474556
申请日：2009-05-29
申请人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
发明人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F11/0724 , G06F11/0772 , G06F21/52 , H04L1/0045 , H04L63/0227
摘要： A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.
摘要翻译：多处理器计算机系统包括多个处理器和多个节点，每个节点包括一个或多个处理器。多个节点中的每一个节点中的本地存储器耦合到每个节点中的处理器，并且包括一个或多个节点的一部分的硬件防火墙可操作以防止来自未授权处理器的写入到本地存储器的写入。

45. 发明授权

US07864792B2 Load balancing for communications within a multiprocessor computer system 有权
标题翻译：多处理器计算机系统内通信的负载平衡
公开(公告)号：US07864792B2
公开(公告)日：2011-01-04
申请号：US12107019
申请日：2008-04-21
申请人： Steven L. Scott , Dennis C. Abts , William J. Dally
发明人： Steven L. Scott , Dennis C. Abts , William J. Dally
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： In a system having a N output ports, wherein N is an integer greater than one, a method of distributing packets across the plurality of output ports. A packet having two or more fields is received and a first number is computed as a function of one or more of the plurality of fields. A second number is computed that is modulo base N of the first number and an output port is selected as a function of the second number.
摘要翻译：在具有N个输出端口的系统中，其中N是大于1的整数，一种在多个输出端口上分发分组的方法。接收具有两个或更多个字段的分组，并且根据多个字段中的一个或多个来计算第一数字。计算第二个数字，其是第一个数字的模数N，并且输出端口被选择为第二个数字的函数。

46. 发明申请

US20100049942A1 DRAGONFLY PROCESSOR INTERCONNECT NETWORK 审中-公开
公开(公告)号：US20100049942A1
公开(公告)日：2010-02-25
申请号：US12195198
申请日：2008-08-20
申请人： John Kim , Dennis C. Abts , Steven L. Scott , William J. Dally
发明人： John Kim , Dennis C. Abts , Steven L. Scott , William J. Dally
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： H04L49/15 , G06F9/45533 , G06F13/4027 , G06F13/4221 , G06F15/17375 , H04L45/28 , H04L45/58 , H04L49/1515 , H04L49/70
摘要： A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.
摘要翻译：多处理器计算机系统包括蜻蜓处理器互连网络，其包括多个处理器节点，多个路由器，每个路由器直接耦合到多个终端节点，彼此耦合并布置成一组的路由器，以及多个组的路由器，使得每个组通过至少一个直接连接连接到彼此组。

47. 发明申请

US20090041049A1 LOAD BALANCING FOR COMMUNICATIONS WITHIN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：用于多处理器计算机系统中的通信的负载平衡
公开(公告)号：US20090041049A1
公开(公告)日：2009-02-12
申请号：US12107019
申请日：2008-04-21
申请人： Steven L. Scott , Dennis C. Abts , William J. Dally
发明人： Steven L. Scott , Dennis C. Abts , William J. Dally
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： In a system having a N output ports, wherein N is an integer greater than one, a method of distributing packets across the plurality of output ports. A packet having two or more fields is received and a first number is computed as a function of one or more of the plurality of fields. A second number is computed that is modulo base N of the first number and an output port is selected as a function of the second number.
摘要翻译：在具有N个输出端口的系统中，其中N是大于1的整数，一种在多个输出端口上分发分组的方法。接收具有两个或更多个字段的分组，并且根据多个字段中的一个或多个来计算第一数字。计算第二个数字，其是第一个数字的模数N，并且输出端口被选择为第二个数字的函数。

48. 发明申请

US20090028172A1 SPECULATIVE FORWARDING IN A HIGH-RADIX ROUTER 有权
标题翻译：高分辨率路由器中的频谱分析
公开(公告)号：US20090028172A1
公开(公告)日：2009-01-29
申请号：US12107036
申请日：2008-04-21
申请人： Steven L. Scott , Gregory Hubbard , Kelly Marquardt , Roger A. Bethard , Dennis C. Abts
发明人： Steven L. Scott , Gregory Hubbard , Kelly Marquardt , Roger A. Bethard , Dennis C. Abts
IPC分类号： H04L12/56
CPC分类号： H04L45/7453 , G06F15/17362 , H04L45/00 , H04L45/28 , H04L45/566 , H04L45/745 , H04L49/15
摘要： A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet.
摘要翻译：一种用于对由路由器接收的分组进行推测转发的系统和方法，其中每个分组包括点对点，并且其中一个或多个点包括循环冗余码（CRC）。接收到一个数据包，并将数据包的phits转发给路由器逻辑。计算分组的循环冗余码，并将其与分组的循环冗余码进行比较。如果循环冗余码不匹配，则会产生错误。如果循环冗余码不匹配，则修改该分组的phit以反映该错误，校正CRC并将校正的CRC与反映CRC错误的phit一起转发到路由器逻辑。在路由器逻辑上，检查数据包是否仍在路由器逻辑内。如果分组仍然在路由器逻辑中，并且出现CRC错误，则丢弃该分组。然而，如果分组不再在路由器逻辑中，并且存在CRC错误，则修改分组，使得下一个路由器丢弃该分组。

49. 发明授权

US07356026B2 Node translation and protection in a clustered multiprocessor system 有权
标题翻译：集群多处理器系统中的节点转换和保护
公开(公告)号：US07356026B2
公开(公告)日：2008-04-08
申请号：US10020854
申请日：2001-12-14
申请人： Steven L. Scott , Chris Dickson , Steve Reinhardt
发明人： Steven L. Scott , Chris Dickson , Steve Reinhardt
IPC分类号： G06F12/00
CPC分类号： G06F12/1072
摘要： A method of node translation for communicating over virtual channels in a clustered multiprocessor system using connection descriptors (CDs), which specify the endpoint nodes for virtual connections. The system includes a local processing element node, a remote processing element node and a network interconnect therebetween for sending communications between the processing element nodes. The method includes assigning a CD to specify an endpoint node for a virtual connection, defining a local connection table (LCT) to be accessed with the CD to produce a system node identifier (SNID) of the endpoint node, generating a communication request including the CD, accessing the LCT using the CD of that communication request to produce the SNID for the endpoint node of the connection in response to that request, and sending a memory request to the endpoint node. The memory request is sent to the local processing element node if the endpoint node is the local processing element node, and is sent over the network interconnect to the remote processing element node if the endpoint node is the remote processing element node.
摘要翻译：一种节点转换方法，用于使用指定虚拟连接的端点节点的连接描述符（CD）在集群多处理器系统中通过虚拟通道进行通信。该系统包括本地处理元件节点，远程处理元件节点及其间的网络互连，用于在处理元件节点之间发送通信。该方法包括分配CD以指定用于虚拟连接的端点节点，定义要用CD访问的本地连接表（LCT）以产生端点节点的系统节点标识符（SNID），生成包括 CD，使用该通信请求的CD访问LCT，以响应于该请求产生连接的端点节点的SNID，以及向端点节点发送存储器请求。如果端点节点是本地处理元件节点，则该存储器请求被发送到本地处理元件节点，并且如果端点节点是远程处理元件节点，则通过网络互连将其发送到远程处理元件节点。

50. 发明授权

US5761706A Stream buffers for high-performance computer memory system 失效
标题翻译：流缓冲区用于高性能计算机内存系统
公开(公告)号：US5761706A
公开(公告)日：1998-06-02
申请号：US333133
申请日：1994-11-01
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Subbarao Palacharla
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Subbarao Palacharla
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines whether a pattern of references has a predetermined relationship, and if so, prefetches stream data into the cache block storage area. Such stream data prefetches are particularly useful in vector processing computers, where once the processor starts to fetch a vector, the addresses of future fetches can be predicted based in the pattern of past fetches. According to various aspects of the present invention, the filtered stream buffer further includes a history table, a validity indicator which is associated with the cache block storage area and indicates which cache blocks, if any, are valid. According to yet another aspect of the present invention, the filtered stream buffer controls random access memory (RAM) chips to stream the plurality of consecutive cache blocks from the RAM into the cache block storage area. According to yet another aspect of the present invention, the stream data includes data for a plurality of strided cache blocks, wherein each of which these strided cache blocks corresponds to an address determined by adding to the first address an integer multiple of the difference between the second address and the first address. According to yet another aspect of the present invention, the processor generates three addresses of data words in the memory, and the filter controller determines whether a predetermined relationship exists among three addresses, and if so, prefetches strided stream data into said cache block storage area.
摘要翻译：耦合到存储器和处理器的经滤波的流缓冲器的方法和装置，并且用于从存储器预取数据。滤波的流缓冲器包括高速缓存块存储区域和过滤器控制器。滤波器控制器确定引用模式是否具有预定关系，如果是，则将流数据预取到高速缓存块存储区域中。这样的流数据预取在向量处理计算机中特别有用，其中一旦处理器开始获取向量，可以基于过去提取的模式来预测未来提取的地址。根据本发明的各个方面，滤波流缓冲器还包括历史表，与高速缓存块存储区相关联的有效性指示符，并指示哪些高速缓存块（如果有的话）是有效的。根据本发明的另一方面，滤波流缓冲器控制随机存取存储器（RAM）芯片以将多个连续高速缓存块从RAM流入高速缓存块存储区域。根据本发明的另一方面，流数据包括用于多个跨度高速缓存块的数据，其中这些跨越高速缓存块中的每一个对应于通过将第一地址相加的确定的地址，第二个地址和第一个地址。根据本发明的另一方面，处理器在存储器中产生数据字的三个地址，并且滤波器控制器确定在三个地址之间是否存在预定的关系，如果是，则将步进流数据预取到所述高速缓存块存储区域。

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