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41. 发明申请

US20130015452A1 ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE 审中-公开
标题翻译：阵列基板和制造阵列基板的方法
公开(公告)号：US20130015452A1
公开(公告)日：2013-01-17
申请号：US13616150
申请日：2012-09-14
申请人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
发明人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1288 , H01L29/42384 , H01L29/78696
摘要： An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
摘要翻译：一种阵列基板，包括：栅极电极和栅极绝缘层，其设置在基底基板上，所述栅极绝缘层在第一区域具有第一厚度，在第二区域具有第二厚度，所述第一厚度大于所述第二厚度; 所述半导体图案设置在所述第一区域中的所述栅极绝缘层上，所述半导体图案的端部相对于所述栅极绝缘层具有阶梯部分; 设置在所述半导体图案上的欧姆接触图案，所述欧姆接触图案的与沟道部分相对的端部与所述半导体图案的端部对准; 以及设置在欧姆接触图案上的源极和漏极，源极和漏极彼此间隔开并且包括第一和第二薄膜晶体管图案。

42. 发明授权

US07982223B2 Display apparatus and method of manufacturing the same 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US07982223B2
公开(公告)日：2011-07-19
申请号：US12372212
申请日：2009-02-17
申请人： Seung-Ha Choi , Min-Seok Oh , Sang-Gab Kim , Hong-Kee Chin , Yu-Gwang Jeong
发明人： Seung-Ha Choi , Min-Seok Oh , Sang-Gab Kim , Hong-Kee Chin , Yu-Gwang Jeong
IPC分类号： H01L29/04 , H01L29/10
CPC分类号： H01L27/124 , G02F1/136286 , G02F2001/136222 , G02F2001/136295 , H01L27/1248 , H01L27/1288
摘要： In a display apparatus and a method of manufacturing the display apparatus, a first insulating layer having a trench and a second insulating layer having a via hole corresponding to the trench are formed on an array substrate. After forming a seed layer in the trench, a conductive layer is formed on the seed layer through a plating process, thereby forming the gate line, the gate electrode and the storage line accommodated in the trench and the via hole.
摘要翻译：在显示装置和显示装置的制造方法中，在阵列基板上形成具有沟槽的第一绝缘层和具有与沟槽对应的通路孔的第二绝缘层。在沟槽中形成晶种层之后，通过电镀工艺在晶种层上形成导电层，从而形成栅极线，栅极电极和容纳在沟槽和通孔中的存储线。

43. 发明申请

US20110097961A1 DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20110097961A1
公开(公告)日：2011-04-28
申请号：US12981287
申请日：2010-12-29
申请人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
发明人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
IPC分类号： H01J9/20
CPC分类号： H01L27/12 , G02F2001/136295 , H01L27/124 , H01L29/458
摘要： In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
摘要翻译：在显示面板和制造显示面板的方法中，在构成显示面板的基板上形成包括与数据线相同材料的栅极线，数据线以及源极和漏极，并且数据线包括铝基合金含有足够的镍以在干蚀刻期间抑制腐蚀。含有AlNi的合金的耐腐蚀性有助于防止在形成这些线和电极的选择性干蚀刻期间数据线，源电极和漏电极的腐蚀。

44. 发明申请

US20110089421A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110089421A1
公开(公告)日：2011-04-21
申请号：US12784376
申请日：2010-05-20
申请人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
发明人： Shin-Il CHOI , Yu-Gwang Jeong , Ki-Yeup Lee , Dong-Ju Yang , Jean-Ho Song
IPC分类号： H01L29/786 , H01L27/12 , H01L21/782
CPC分类号： H01L27/124 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.
摘要翻译：薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法晶体管防止在信号线上形成异物。

45. 发明申请

US20110062445A1 DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US20110062445A1
公开(公告)日：2011-03-17
申请号：US12952744
申请日：2010-11-23
申请人： Min-Seok OH , Bong-Kyu SHIN , Sang-Gab KIM , Eun-Guk LEE , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
发明人： Min-Seok OH , Bong-Kyu SHIN , Sang-Gab KIM , Eun-Guk LEE , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
IPC分类号： H01L29/739
CPC分类号： G02F1/136227 , G02F1/13439 , G02F2201/50
摘要： A method of forming a display substrate includes forming an array layer on a substrate, forming a passivation layer on the array layer, forming a photoresist pattern on the passivation layer corresponding to a gate line, a source line and a thin-film transistor of the array layer, etching the passivation layer using the photoresist pattern as a mask, Non-uniformly surface treating a surface of the photoresist pattern, forming a transparent electrode layer on the substrate having the surface-treated photoresist pattern formed thereon and forming a pixel electrode. The forming a pixel electrode includes removing the photoresist pattern and the transparent electrode layer, such as by infiltrating a strip solution into the surface-treated photoresist pattern.
摘要翻译：形成显示基板的方法包括在基板上形成阵列层，在阵列层上形成钝化层，在对应于栅极线，源极线和薄膜晶体管的钝化层上形成光致抗蚀剂图案使用光致抗蚀剂图案作为掩模蚀刻钝化层，对光致抗蚀剂图案的表面进行不均匀的表面处理，在其上形成有表面处理的光致抗蚀剂图案的基板上形成透明电极层并形成像素电极。形成像素电极包括通过将带状溶液浸入表面处理的光致抗蚀剂图案中去除光致抗蚀剂图案和透明电极层。

46. 发明申请

US20110024752A1 THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：薄膜晶体管，其制造方法和显示装置
公开(公告)号：US20110024752A1
公开(公告)日：2011-02-03
申请号：US12900634
申请日：2010-10-08
申请人： Shin-Il CHOI , Sang-Gab KIM , Hong-Kee CHIN , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI
发明人： Shin-Il CHOI , Sang-Gab KIM , Hong-Kee CHIN , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI
IPC分类号： H01L29/16 , H01L33/16
CPC分类号： H01L27/124 , H01L29/458 , H01L29/66765
摘要： A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer.
摘要翻译：一种薄膜晶体管的制造方法，包括在基板上形成栅电极，在栅电极上形成半导体层，在半导体层上形成源电极，在与源电极间隔开的半导体层上形成漏电极，在源电极和漏电极上形成铜层图案，将源电极和漏电极上的铜层图案暴露于含氟处理气体，以在其上形成氟化铜层图案，并对该半导体层进行构图。

47. 发明申请

US20100308334A1 ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE 有权
标题翻译：阵列基板和制造阵列基板的方法
公开(公告)号：US20100308334A1
公开(公告)日：2010-12-09
申请号：US12777347
申请日：2010-05-11
申请人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
发明人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
IPC分类号： H01L33/16 , H01L21/336
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1288 , H01L29/42384 , H01L29/78696
摘要： An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
摘要翻译：一种阵列基板，包括：栅极电极和栅极绝缘层，其设置在基底基板上，所述栅极绝缘层在第一区域具有第一厚度，在第二区域具有第二厚度，所述第一厚度大于所述第二厚度; 所述半导体图案设置在所述第一区域中的所述栅极绝缘层上，所述半导体图案的端部相对于所述栅极绝缘层具有阶梯部分; 设置在所述半导体图案上的欧姆接触图案，所述欧姆接触图案的与沟道部分相对的端部与所述半导体图案的端部对准; 以及设置在欧姆接触图案上的源极和漏极，源极和漏极彼此间隔开并且包括第一和第二薄膜晶体管图案。

48. 发明申请

US20090278126A1 METAL LINE SUBSTRATE, THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：金属线基板，薄膜晶体管基板及其形成方法
公开(公告)号：US20090278126A1
公开(公告)日：2009-11-12
申请号：US12431969
申请日：2009-04-29
申请人： Dong-Ju YANG , Sang-Gab KIM , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
发明人： Dong-Ju YANG , Sang-Gab KIM , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
IPC分类号： H01L29/786 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76879 , H01L27/124
摘要： A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the insulating substrate, and a low-resistive conductive layer pattern disposed in the trench and contacting the seed layer pattern. The capping layer pattern includes a protrusion region which is in contact with the low-resistive conductive layer pattern.
摘要翻译：一种金属线基板及其制造方法，所述金属线基板包括绝缘层和设置在绝缘基板上的覆盖层，由绝缘层限定的沟槽和设置在绝缘基板上的覆盖层，种子层图案设置在绝缘基板上，以及设置在沟槽中并接触种子层图案的低电阻导电层图案。覆盖层图案包括与低电阻导电层图案接触的突起区域。

49. 发明申请

US20090152635A1 THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING A DISPLAY PANEL 有权
标题翻译：薄膜晶体管和制造显示面板的方法
公开(公告)号：US20090152635A1
公开(公告)日：2009-06-18
申请号：US12331361
申请日：2008-12-09
申请人： Yu-Gwang JEONG , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
发明人： Yu-Gwang JEONG , Young-Wook Lee , Sang-Gab Kim , Woo-Geun Lee , Min-Seok Oh , Jang-Soo Kim , Kap-Soo Yoon , Shin-Il Choi , Hong-Kee Chin , Seung-Ha Choi , Seung-Hwan Shim , Sung-Hoon Yang , Ki-Hun Jeong
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1259 , H01L27/1288 , H01L29/66765
摘要： Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.
摘要翻译：本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成保护构件和保护构件的相应侧上的欧姆接触。因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

50. 发明申请

US20080093334A1 METHOD OF PRODUCING THIN FILM TRANSISTOR SUBSTRATE 审中-公开
标题翻译：生产薄膜晶体管基板的方法
公开(公告)号：US20080093334A1
公开(公告)日：2008-04-24
申请号：US11874098
申请日：2007-10-17
申请人： Seung-ha Choi , Sang-gab Kim , Min-seok Oh , Shin-il Choi , Dae-ok Kim , Hong-kee Chin , Young-ho Jeong , Yu-gwang Jeong
发明人： Seung-ha Choi , Sang-gab Kim , Min-seok Oh , Shin-il Choi , Dae-ok Kim , Hong-kee Chin , Young-ho Jeong , Yu-gwang Jeong
IPC分类号： H01B13/00
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method of producing a thin film transistor substrate to prevent an interconnection from being corroded during a dry etching process includes sequentially forming on an insulating substrate a gate interconnection, a gate insulating layer, an active layer, a conductive layer for a data interconnection, and a photoresist pattern including a first region and a second region, etching the conductive layer for the data interconnection using the photoresist pattern as an etching mask to form a conductive layer pattern for source/drain electrodes, etching the active layer using the photoresist pattern as the etching mask to form an active layer pattern, removing the second region of the photoresist pattern, dry etching the conductive layer pattern for the source/drain electrodes under the second region using the photoresist pattern as the etching mask and etching gas, etching a portion of the active layer pattern using the photoresist pattern as the etching mask, and physically removing the reaction byproduct using a reaction byproduct removal agent so that external force is applied to the etching gas and the reaction byproduct of the conductive layer pattern for the source/drain electrodes.
摘要翻译：制造薄膜晶体管基板以防止在干法蚀刻工艺中被互连的腐蚀的方法包括：在绝缘基板上依次形成栅极互连，栅极绝缘层，有源层，用于数据互连的导电层，以及包括第一区域和第二区域的光致抗蚀剂图案，使用光致抗蚀剂图案蚀刻用于数据互连的导电层作为蚀刻掩模，以形成用于源/漏电极的导电层图案，使用光致抗蚀剂图案蚀刻活性层作为蚀刻掩模以形成有源层图案，去除光致抗蚀剂图案的第二区域，使用光致抗蚀剂图案作为蚀刻掩模和蚀刻气体，在第二区域下干蚀刻用于源/漏电极的导电层图案，蚀刻部分使用光致抗蚀剂图案作为蚀刻掩模的有源层图案，并物理去除r 使用反应副产物除去剂的副产物使得外力施加到蚀刻气体和用于源/漏电极的导电层图案的反应副产物。

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