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    • 41. 发明授权
    • Method and system for reducing required storage during decompression of a compressed file
    • 在压缩文件解压缩期间减少所需存储的方法和系统
    • US07924183B2
    • 2011-04-12
    • US12464628
    • 2009-05-12
    • Jian GuiHong Jie NieJohn TurekWei Ying YuYong Zheng
    • Jian GuiHong Jie NieJohn TurekWei Ying YuYong Zheng
    • H03M7/30
    • G06F17/30067
    • A method and system for decompressing a compressed file is disclosed in this invention, the method comprising: reading a compressed data block from the compressed file; decompressing the compressed data block; outputting the decompressed data for storage into a decompressed file; deleting the compressed data block that was decompressed from the compressed file. The proposed method and system in this invention can reduce the unnecessary repeated data between compressed data and decompressed data. The storage space requirement will be reduced during decompression, and the existing compression/decompression algorithms need not be changed by using this invention. Thus, this invention is easy to be integrated into existing compression/decompression tools.
    • 在本发明中公开了一种解压缩压缩文件的方法和系统,该方法包括:从压缩文件读取压缩数据块; 解压缩压缩数据块; 将解压缩的数据输出到解压缩文件中; 删除从压缩文件解压缩的压缩数据块。 本发明提出的方法和系统可以减少压缩数据和解压缩数据之间不必要的重复数据。 在解压缩期间存储空间需求将减少,并且现有的压缩/解压缩算法不需要通过使用本发明来改变。 因此,本发明易于集成到现有的压缩/减压工具中。
    • 42. 发明申请
    • Word Line Decoder Circuit Apparatus and Method
    • 字线解码器电路设备及方法
    • US20110069571A1
    • 2011-03-24
    • US12816960
    • 2010-06-16
    • Shin-Jang ShenBo-Chang WuChuan Ying YuKen-Hui ChenKuen-Long ChangChun-Hsiung Hung
    • Shin-Jang ShenBo-Chang WuChuan Ying YuKen-Hui ChenKuen-Long ChangChun-Hsiung Hung
    • G11C7/00G11C8/10
    • G11C16/16
    • One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
    • 该技术的一个实施例是一种装置,存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中,该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制,以在擦除操作期间确定反相器的输入值。
    • 43. 发明授权
    • Absolute time delay generating device
    • 绝对延时发生装置
    • US07825713B2
    • 2010-11-02
    • US12286765
    • 2008-10-02
    • Chen-Yi LeeJui-Yuan YuChien-Ying YuJuinn-Ting Chen
    • Chen-Yi LeeJui-Yuan YuChien-Ying YuJuinn-Ting Chen
    • H03H11/26
    • G06F1/14
    • An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.
    • 绝对时间延迟产生装置包括PVT(过程电压 - 温度)检测装置和延迟定时发生器。 PVT检测装置至少包括延迟模块和信号相位/频率控制模块。 延迟模块包括控制单元和参考单元。 控制单元与PVT的延迟属性的灵敏度不同于参考单元。 延迟模块比较原点信号分别通过控制单元和参考单元产生的相位或频率差,并产生延迟模块的延迟参数。 信号相位/频率控制模块接收并比较延迟参数以确定绝对时间延迟产生装置的环境PVT条件,以便控制和校正延迟定时发生器从而产生精确的绝对时间延迟。 在各种PVT影响下,绝对时间延迟产生装置能够产生精确的绝对时间信号。
    • 46. 发明申请
    • PLIERS HAVING GREATER HOLDING FORCE
    • 具有较大保持力的钢笔
    • US20090133540A1
    • 2009-05-28
    • US11945586
    • 2007-11-27
    • CHIU-YING YU
    • CHIU-YING YU
    • B25B13/28
    • B25B13/28B25B13/505
    • A pair of pliers include a shank, a fixed jaw locked onto the shank, and a movable jaw pivotally mounted on the shank and movable relative to the fixed jaw. Thus, the first contact point of the locking teeth of the fixed jaw and the second contact point of the first engaging teeth of the first toothed face of the movable jaw have a larger friction with a workpiece by a special angle design of the fixed jaw and the movable jaw to enhance the clamping force of the fixed jaw and the movable jaw on the workpiece, so that the workpiece is clamped by the fixed jaw and the movable jaw exactly and closely to prevent the workpiece from being slipped from the fixed jaw and the movable jaw during operation of the pliers.
    • 一对钳子包括柄,锁定在柄上的固定爪,以及枢转地安装在柄上并相对于固定夹爪可移动的可动钳。 因此,固定夹爪的锁定齿的第一接触点和可动夹爪的第一齿面的第一接合齿的第二接触点通过固定夹爪的特殊角度设计与工件具有较大的摩擦力,并且 活动夹爪,增加固定夹爪和工件上的可动夹爪的夹持力,使工件被固定夹爪和可动夹钳精确而紧密地夹紧,防止工件从固定夹爪上滑落, 钳子操作过程中的活动钳口。