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41. 发明授权

US08717002B2 Constant on-time converter and control method thereof 有权
标题翻译：恒定导通时间转换器及其控制方法
公开(公告)号：US08717002B2
公开(公告)日：2014-05-06
申请号：US13538045
申请日：2012-06-29
申请人： Xiaoyu Xi
发明人： Xiaoyu Xi
IPC分类号： H02M3/156
CPC分类号： H02M3/158 , H02M2001/0003
摘要： A constant ON-time converter is disclosed. The constant ON-time converter comprises a feedback circuit, a slope compensation circuit and a buffer circuit. The feedback signal comprises an output configured to provide a feedback signal indicating an output voltage of the constant ON-time converter. The slope compensation circuit comprises an output configured to provide a slope compensation signal. The buffer circuit is coupled between the output of the feedback circuit and the output of the slope compensation circuit to avoid the feedback signal and the output voltage of the constant ON-time converter is influenced by the slope compensation signal.
摘要翻译：公开了一种恒定的导通时间转换器。恒定导通时间转换器包括反馈电路，斜率补偿电路和缓冲电路。反馈信号包括被配置为提供指示恒定导通时间转换器的输出电压的反馈信号的输出。斜率补偿电路包括被配置为提供斜率补偿信号的输出。缓冲电路耦合在反馈电路的输出和斜坡补偿电路的输出之间，以避免反馈信号，并且恒定导通时间转换器的输出电压受斜率补偿信号的影响。

42. 发明申请

US20120287682A1 SWITCH MODE POWER SUPPLY AND CONTROL METHOD THEREOF 有权
标题翻译：开关电源及其控制方法
公开(公告)号：US20120287682A1
公开(公告)日：2012-11-15
申请号：US13468706
申请日：2012-05-10
申请人： Yongliang Zhang , Xiaoyu Xi , Jiali Cai
发明人： Yongliang Zhang , Xiaoyu Xi , Jiali Cai
IPC分类号： H02M3/335
CPC分类号： H02M3/33507 , H05B33/0815 , Y02B20/341
摘要： In one embodiment, a switch mode power supply comprising a switch and a control circuit is disclosed. The control circuit may comprise a multi-function pin configured to receive a first current sampling signal and a first voltage sampling signal. A first comparing signal may be provided by comparing the first voltage sampling signal with a first threshold signal when the switch is turned OFF, and a second comparing signal may be provided by comparing the first current sampling signal with a second threshold signal when the switch is turned ON. The control circuit may be configured to control the switch in accordance with the first comparing signal and the second comparing signal.
摘要翻译：在一个实施例中，公开了一种包括开关和控制电路的开关模式电源。控制电路可以包括被配置为接收第一电流采样信号和第一电压采样信号的多功能引脚。可以通过在开关断开时将第一电压采样信号与第一阈值信号进行比较来提供第一比较信号，并且可以通过将第一电流采样信号与第二阈值信号进行比较来提供第二比较信号，当开关为打开。控制电路可以被配置为根据第一比较信号和第二比较信号来控制开关。

43. 发明申请

US20100227576A1 CONTROLLING A VOLTAGE REGULATOR 有权
标题翻译：控制电压调节器
公开(公告)号：US20100227576A1
公开(公告)日：2010-09-09
申请号：US12783193
申请日：2010-05-19
申请人： Xiaoyu Xi , Shyam S. Somayajula
发明人： Xiaoyu Xi , Shyam S. Somayajula
IPC分类号： H04B1/04
CPC分类号： H02M3/156
摘要： A wireless system includes a radio and a voltage regulator, which provides a supply voltage to the radio. The voltage regulator includes a storage element, at least one switch that is coupled to the storage element and a controller. The controller operates the voltage regulator in a continuous mode of operation, operates the voltage regulator in a discontinuous mode of operation in response to an output current of the voltage regulator decreasing below a predetermined threshold; operates the switch(es) to energize the storage element in response to a detection of whether an output voltage is below a threshold level; operates the switch(es) to halt the energization of the storage element in response to detecting a current in the storage element reaching a predetermined current threshold; operates the switch(es) to energize and de-energize the storage element in the discontinuous mode of operation; and operates the switch(es) to energize the storage element in synchronization with a periodic clock signal.
摘要翻译：无线系统包括向无线电提供电源电压的无线电和电压调节器。电压调节器包括存储元件，耦合到存储元件的至少一个开关和控制器。所述控制器在连续工作模式下操作所述电压调节器，响应于所述电压调节器的输出电流降低到预定阈值以下，以不连续工作模式操作所述电压调节器; 响应于检测输出电压是否低于阈值水平，操作开关以使存储元件通电; 响应于检测到存储元件中的电流达到预定电流阈值，操作开关以停止存储元件的通电; 操作开关以在不连续操作模式下对存储元件通电和断电; 并且操作该开关以与周期性时钟信号同步地激励存储元件。

44. 发明申请

US20070075698A1 Management of regulator-induced switching noise for sampled systems 有权
标题翻译：对采样系统调节器引起的开关噪声的管理
公开(公告)号：US20070075698A1
公开(公告)日：2007-04-05
申请号：US11240745
申请日：2005-09-30
申请人： Xiaoyu Xi , Shyam Somayajula
发明人： Xiaoyu Xi , Shyam Somayajula
IPC分类号： G05F1/00
CPC分类号： H02M1/44 , G06F1/26
摘要： A system includes a sampler to sample an input voltage and a switching regulator. The switching regulator is adapted to regulate a switching operation of the regulator in response to the sampling by the sampler.
摘要翻译：系统包括用于对输入电压进行采样的采样器和开关调节器。开关调节器适于响应于采样器的采样来调节调节器的开关操作。

45. 发明申请

US20060227477A1 Undervoltage detection circuit 失效
标题翻译：欠压检测电路
公开(公告)号：US20060227477A1
公开(公告)日：2006-10-12
申请号：US11094610
申请日：2005-03-30
申请人： Wenjun Sheng , Xiaoyu Xi
发明人： Wenjun Sheng , Xiaoyu Xi
IPC分类号： H02H3/24
CPC分类号： G01R19/16552
摘要： An undervoltage detection circuit includes a first transistor and a second transistor coupled to a supply voltage node and arranged to form a current mirror. The undervoltage detection circuit also includes a first bipolar transistor and a second bipolar transistor. A collector of the first bipolar transistor is coupled to the first transistor, and an emitter of the first bipolar transistor is coupled to a reference voltage node. A collector of the second bipolar transistor is coupled to the second transistor and an emitter of the second bipolar transistor is coupled to the reference voltage node through a first resistor. The undervoltage detection circuit further includes a third transistor coupled through a second resistor to an input voltage node. An output signal indicative of an input voltage is derived from a voltage established at the collector of the second bipolar transistor.
摘要翻译：欠压检测电路包括耦合到电源电压节点并被布置成形成电流镜的第一晶体管和第二晶体管。欠压检测电路还包括第一双极晶体管和第二双极晶体管。第一双极晶体管的集电极耦合到第一晶体管，并且第一双极晶体管的发射极耦合到参考电压节点。第二双极晶体管的集电极耦合到第二晶体管，并且第二双极晶体管的发射极通过第一电阻耦合到参考电压节点。欠压检测电路还包括通过第二电阻器耦合到输入电压节点的第三晶体管。指示输入电压的输出信号是从在第二双极晶体管的集电极处建立的电压导出的。

46. 发明授权

US06809590B1 Output stage using positive feedback to provide large current sourcing capability 有权
标题翻译：输出级使用正反馈提供大电流采样能力
公开(公告)号：US06809590B1
公开(公告)日：2004-10-26
申请号：US10436010
申请日：2003-05-12
申请人： Kae Wong , Xiaoyu Xi
发明人： Kae Wong , Xiaoyu Xi
IPC分类号： H03F326
CPC分类号： H03F3/345 , H03F1/342
摘要： An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by the output current source IOUT that is desired to be increased. Without positive feedback, the gate of MN2 would be fixed by MP1 and MN1, and when input voltage VIN decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP2's VGS but also in the VGS of another transistor MN2; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in IOUT. However, if positive feedback such as MP5 is provided, the feedback dynamically increases the voltage at the gate of MN2. The increased voltage of MN2's gate essentially provides more voltage “headroom” for MP2 and MN2, and allows current through MP2 to increase with any voltage decrease in VIN. Through current mirroring, the increased current through MP2 ultimately results in the desired higher maximum output current source IOUT. This increase in output current sourcing is achieved with a minimal additional circuitry—a single transistor, MP5. The feedback is local (internal to the output stage), so that loop delay is minimal and response is fast. Further, because of improved DC gain within the output stage, the increased maximum IOUT is achieved without compromising other circuit parameters such as power supply rejection ratio (PSRR).
摘要翻译：输出级通过局部正反馈技术提供增加的电流源功能。通过晶体管MP2的电流被希望增加的输出电流源IOUT镜像。没有正反馈，MN2的门将由MP1和MN1固定，并且当输入电压VIN降低增量电压DeltaV时，所产生的电流增加将不仅在MP2的VGS上分配增加的电压，而且还会在另一晶体管的VGS中分配增加的电压 MN2; 因此，不是所有的DeltaV电压变化都不会在IOUT中被镜像。然而，如果提供诸如MP5的正反馈，则反馈动态地增加MN2的门处的电压。 MN2门的电压增加对MP2和MN2基本上提供了更多的电压“余量”，并且允许通过MP2的电流随着VIN中的任何电压降低而增加。通过电流镜像，通过MP2的增加的电流最终导致所需的更高的最大输出电流源IOUT。输出电流源的增加通过最小的附加电路实现 - 单个晶体管MP5。反馈是本地的（输出级内部），使得回路延迟最小，响应快。此外，由于在输出级内改善了直流增益，所以实现了增加的最大IOUT，而不会影响其他电路参数，如电源抑制比（PSRR）。

47. 发明授权

US06677735B2 Low drop-out voltage regulator having split power device 有权
标题翻译：具有分离功率器件的低压差稳压器
公开(公告)号：US06677735B2
公开(公告)日：2004-01-13
申请号：US10024397
申请日：2001-12-18
申请人： Xiaoyu Xi
发明人： Xiaoyu Xi
IPC分类号： G05F140
CPC分类号： G05F1/575
摘要： The present invention provides a low drop-out voltage regulator (200) that reduces gate capacitance and simplifies the compensation needed to maintain stability, without requiring additional and/or larger Miller capacitors (108), by splitting the output (220, 221) of the driver (112A) for different operational modes, selectively driving a small power device (206), a large power device (214) or both based on the mode.
摘要翻译：本发明提供了一种降低栅极电容并简化维持稳定所需的补偿的低压差稳压器（200），而不需要额外的和/或更大的米勒电容器（108），通过将输出（220,221）分开用于不同操作模式的驱动器（112A），基于该模式选择性地驱动小功率设备（206），大功率设备（214）或两者。

48. 发明授权

US06541946B1 Low dropout voltage regulator with improved power supply rejection ratio 有权
标题翻译：低压差稳压器，具有改善的电源抑制比
公开(公告)号：US06541946B1
公开(公告)日：2003-04-01
申请号：US10102501
申请日：2002-03-19
申请人： Jun Chen , Xiaoyu Xi
发明人： Jun Chen , Xiaoyu Xi
IPC分类号： G05F140
CPC分类号： G05F1/575
摘要： The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier 20 having a first input coupled to a reference voltage node Vref; a second amplifier 22 having an input coupled to an output of the first amplifier 20; a pass transistor 24 having a control node coupled to an output of the second amplifier 22; a feedback circuit 26 and 28 having an input coupled to the pass transistor 24 and an output coupled to a second input of the first amplifier 20; an inverting gain stage 36 coupled to the input of the second amplifier 22; and a high pass filter 42, 44, and 38 coupled between a power supply node and a control node of the inverting gain stage 36. The circuit uses the high pass filter 42, 44, and 38 and inverting gain stage 36 to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node Vo.
摘要翻译：具有改善的电源抑制比的低压差稳压器（LDO）电路包括：具有耦合到参考电压节点Vref的第一输入的第一放大器20; 具有耦合到第一放大器20的输出的输入的第二放大器22; 具有耦合到第二放大器22的输出的控制节点的传输晶体管24; 具有耦合到传输晶体管24的输入和耦合到第一放大器20的第二输入的输出的反馈电路26和28; 耦合到第二放大器22的输入的反相增益级36; 以及耦合在电源节点和反相增益级36的控制节点之间的高通滤波器42,44和38.该电路使用高通滤波器42,44和38以及反相增益级36来馈送功率将LDO的控制回路中的纹波提供给输出节点Vo的电源纹波的影响。

49. 发明授权

US06246221B1 PMOS low drop-out voltage regulator using non-inverting variable gain stage 有权
标题翻译： PMOS低压差稳压器使用非反相可变增益级
公开(公告)号：US06246221B1
公开(公告)日：2001-06-12
申请号：US09665816
申请日：2000-09-20
申请人： Xiaoyu Xi
发明人： Xiaoyu Xi
IPC分类号： G05F140
CPC分类号： G05F1/575
摘要： A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The non-inversion variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with the loop formed by the compensation capacitor is kept substantially constant.
摘要翻译：使用输出PMOS通道器件的高电源纹波抑制（PSRR）内部补偿低压差稳压器。电压调节器使用非反相可变增益放大器级来响应于通过输出PMOS器件的负载电流来调节其增益，使得当负载电流减小时，增益增加，其中与电压调节器相关联的第二极点为超过与电压调节器相关联的单位增益频率。非反相可变增益放大器进一步可操作以响应于通过功率PMOS器件的负载电流来调节其增益，使得当负载电流增加时，增益减小，其中与形成的环路相关联的电压调节器单位增益带宽由补偿电容器保持基本恒定。

50. 发明授权

US5982309A Parallel-to-serial CMOS data converter with a selectable bit width mode D flip-flop M matrix 失效
标题翻译：并行至串行CMOS数据转换器，具有可选位宽模式D触发器M矩阵
公开(公告)号：US5982309A
公开(公告)日：1999-11-09
申请号：US5080
申请日：1998-01-09
申请人： Xiaoyu Xi , William C. Black, Jr.
发明人： Xiaoyu Xi , William C. Black, Jr.
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.
摘要翻译：高速并行至串行CMOS数据发射器使用D触发器矩阵结构将移位方案与选择方案组合以串行化并行位数据。数据通过多个数据路径以较低的频率部分序列化，时分复用方案从每个数据路径中选择一个位，允许流水线数据处理。 CMOS架构使用选择性负载时钟模式切换，允许通过调整加载时钟的频率来简单地处理不同的字位宽度。

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