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41. 发明授权

US5670412A Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate 失效
标题翻译：在半导体衬底上形成场氧化区的半导体加工方法
公开(公告)号：US5670412A
公开(公告)日：1997-09-23
申请号：US506172
申请日：1995-07-25
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32 , Y10S438/911
摘要： A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Ge.sub.x Si.sub.y layer over the pad oxide layer, where x is greater than 0.2, y is from 0 to 0.8, and x+y=1.0; c) providing a patterned nitride oxidation masking layer over the Ge.sub.x Si.sub.y layer to define at least one pair of adjacent nitride masking blocks overlying desired active area regions of the substrate; d) etching exposed portions of the Ge.sub.x Si.sub.y layer and thereby defining exposed sidewall edges of the Ge.sub.x Si.sub.y layer; e) providing an oxidation restriction layer over the respective Ge.sub.x Si.sub.y sidewalls, the oxidation restriction layer restricting rate of oxidation of the Ge.sub.x Si.sub.y layer from what would otherwise occur if the oxidation restriction layer were not present; f) oxidizing portions of the substrate unmasked by the masking layer to form at least one pair of adjacent SiO.sub.2 substrate field oxide regions; g) stripping the patterned masking layer from the substrate; h) after stripping the masking layer, stripping the Ge.sub.x Si.sub.y layer or any oxidation product therefrom from the substrate selectively relative to SiO.sub.2 ; and i) after stripping the Ge.sub.x Si.sub.y layer or any oxidation product, stripping the pad oxide and any other oxide from the substrate between the pair of adjacent field oxide regions to outwardly expose substrate active area between the pair of field oxide regions. The invention also contemplates products produced by such method.
摘要翻译：形成场氧化物区域的半导体处理方法包括：a）在半导体衬底上提供牺牲衬垫氧化物层; b）在衬垫氧化物层上提供GexSiy层，其中x大于0.2，y为0至0.8，x + y = 1.0; c）在所述GexSiSi层上提供图案化的氮化物氧化掩蔽层以限定覆盖所述衬底的期望有源区域区域的至少一对相邻氮化物掩模块; d）蚀刻GexSiy层的暴露部分，从而限定GexSiy层的暴露的侧壁边缘; e）在相应的GexSiy侧壁上提供氧化限制层，所述氧化限制层限制GexSiy层与不存在氧化限制层时会发生的氧化的速率; f）氧化由掩模层未掩蔽的衬底的部分以形成至少一对相邻的SiO 2衬底场氧化物区域; g）从衬底剥离图案化掩模层; h）在剥离掩蔽层之后，相对于SiO 2选择性地从衬底上剥离GexSiy层或其任何氧化产物; 以及i）在剥离GexSiy层或任何氧化产物之后，在该对相邻的场氧化物区域之间剥离衬垫氧化物和任何其它氧化物，以向外暴露一对场氧化物区域之间的衬底有源区。本发明还考虑了通过这种方法生产的产品。

42. 发明授权

US08557656B2 Cross-hair cell based floating body device 有权
标题翻译：基于跨毛细胞的浮体装置
公开(公告)号：US08557656B2
公开(公告)日：2013-10-15
申请号：US13584590
申请日：2012-08-13
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/8242
CPC分类号： H01L29/7841 , H01L27/10802 , H01L27/10826 , H01L29/785
摘要： A non-planar transistor having floating body structures and methods for fabricating the same are disclosed. In certain embodiments, the transistor includes a fin having upper and lower doped regions. The upper doped regions may form a source and drain separated by a shallow trench formed in the fin. During formation of the fin, a hollow region may be formed underneath the shallow trench, isolating the source and drain. An oxide may be formed in the hollow region to form a floating body structure, wherein the source and drain are isolated from each other and the substrate formed below the fin. In some embodiments, independently bias gates may be formed adjacent to walls of the fin. In other embodiments, electrically coupled gates may be formed adjacent to the walls of the fin.
摘要翻译：公开了一种具有浮体结构的非平面晶体管及其制造方法。在某些实施例中，晶体管包括具有上和下掺杂区的鳍。上掺杂区域可以形成由在鳍片中形成的浅沟槽分离的源极和漏极。在翅片形成期间，可以在浅沟槽下方形成中空区域，隔离源极和漏极。可以在中空区域中形成氧化物以形成浮体结构，其中源极和漏极彼此隔离，并且形成在鳍下方的衬底。在一些实施例中，独立的偏置门可以邻近翅片的壁形成。在其他实施例中，电耦合栅极可以形成为邻近翅片的壁。

43. 发明授权

US08497550B2 Multi-level DRAM cell using CHC technology 有权
标题翻译：使用CHC技术的多级DRAM单元
公开(公告)号：US08497550B2
公开(公告)日：2013-07-30
申请号：US13046798
申请日：2011-03-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76
CPC分类号： G11C11/4097 , G11C11/565 , H01L27/108 , H01L27/10826 , H01L29/785
摘要： A DRAM memory cell includes: a first finFET structure; and a second finFET structure adjacent to the first finFET structure. The second finFET structure includes: a source follower transistor in a first fin of the second finFET structure; an access transistor in a second fin of the second fin FET structure; a write word line; and a read word line stacked above the write word line. When the read word line is fired high, the source follower transistor enables data to be read from the first finFET structure.
摘要翻译： DRAM存储单元包括：第一finFET结构; 以及与第一finFET结构相邻的第二finFET结构。第二finFET结构包括：第二鳍状结构的第一鳍中的源极跟随器晶体管; 第二鳍式FET结构的第二鳍中的存取晶体管; 写字线以及堆叠在写字线之上的读字线。当读取的字线被激发为高电平时，源极跟随器晶体管使得能够从第一finFET结构读取数据。

44. 发明授权

US08450785B2 Systems and devices including multi-gate transistors and methods of using, making, and operating the same 有权
标题翻译：包括多栅极晶体管的系统和器件及其使用，制造和操作的方法
公开(公告)号：US08450785B2
公开(公告)日：2013-05-28
申请号：US13183337
申请日：2011-07-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L27/088 , H01L29/78
CPC分类号： H01L27/108 , H01L21/845 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L28/91 , H01L29/66795 , H01L29/7851
摘要： Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array.
摘要翻译：公开了形成晶体管的方法。在一个实施例中，通过在衬底中形成多个椭圆形基底并形成椭圆形基底形成翅片来形成晶体管。晶体管形成在鳍内，使得它们可以用作存储器阵列中的存取装置。

45. 发明授权

US08399920B2 Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls 有权
标题翻译：半导体器件包括具有多个垂直取向侧壁的晶体管栅极
公开(公告)号：US08399920B2
公开(公告)日：2013-03-19
申请号：US11863535
申请日：2007-09-28
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/76
CPC分类号： H01L29/4236 , H01L21/26586 , H01L29/42368 , H01L29/66621 , H01L29/66659 , H01L29/78 , H01L29/7834
摘要： A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.
摘要翻译：用于制造凹陷存取器晶体管栅极的方法具有增加的掩模未对准的容限。本发明的一个实施例包括在半导体晶片上形成垂直间隔层，然后蚀刻垂直间隔层和半导体晶片以在晶片中形成凹陷。然后在沟槽内和垂直间隔层上形成导电晶体管栅极层。蚀刻晶体管栅极层，暴露垂直间隔层。在蚀刻的导电栅极层上方并在垂直间隔层之上形成间隔层，然后间隔层和垂直间隔层被各向异性地蚀刻。在各向异性蚀刻垂直间隔层之后，垂直间隔层的一部分在垂直于半导体晶片的主表面的平面的方向插入在半导体晶片和蚀刻的导电晶体管栅极层之间。

46. 发明授权

US08384142B2 Non-planar thin fin transistor 有权
标题翻译：非平面薄鳍晶体管
公开(公告)号：US08384142B2
公开(公告)日：2013-02-26
申请号：US13193363
申请日：2011-07-28
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L27/108 , H01L21/00 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing.
摘要翻译：制造非平面晶体管的方法。翅片场效应晶体管（finFET）通常围绕翅片（例如，高，薄的半导体构件）构建。在制造过程中，翅片可能会遇到各种机械应力，例如在基体运动期间的惯性力和清洁步骤期间的流体力。如果翅片上的力太大，则翅片可能会断裂，并可能导致晶体管不起作用。在形成翅片的第二面之前支撑翅片的一侧在翅片结构中产生稳定性，从而抵消在制造过程中产生的许多机械应力。

47. 发明授权

US08372710B2 Vertical transistors 有权
标题翻译：垂直晶体管
公开(公告)号：US08372710B2
公开(公告)日：2013-02-12
申请号：US13329977
申请日：2011-12-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L29/7827 , H01L27/1052 , H01L27/10823 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L29/66621 , H01L29/78
摘要： A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.
摘要翻译：具有U形晶体管的半导体结构包括由衬底中的交叉沟槽限定的柱对的顶部的源/漏区域。一个支柱通过在周围的沟槽上方延伸的脊连接到一对中的另一个柱。柱的脊和下部在U形结构的相对侧限定U形通道，面对在那些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。还公开了形成半导体结构的方法。

48. 发明申请

US20130005102A1 Data Cells with Drivers and Methods of Making and Operating the Same 有权
公开(公告)号：US20130005102A1
公开(公告)日：2013-01-03
申请号：US13612361
申请日：2012-09-12
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： G11C11/40 , H01L27/105 , H01L27/10814 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/785
摘要： Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

49. 发明授权

US08294511B2 Vertically stacked fin transistors and methods of fabricating and operating the same 有权
标题翻译：垂直堆叠鳍式晶体管及其制造和操作方法
公开(公告)号：US08294511B2
公开(公告)日：2012-10-23
申请号：US12950761
申请日：2010-11-19
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L25/00
CPC分类号： H01L21/823431 , H01L27/0886 , H01L27/10826 , H01L27/10879
摘要： A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.
摘要翻译：公开了一种在半导体鳍片中垂直堆叠（也称为垂直偏移）晶体管的半导体器件。半导体鳍片可以包括由第一沟槽分离并且在鳍片的第一掺杂区域中具有源极和漏极的下部晶体管。半导体鳍片还包括垂直偏离第一晶体管并由第二沟槽隔开的上晶体管，并且在鳍片的第二掺杂区域中具有源极和漏极。上和下堆叠栅极可以设置在翅片的侧壁上，使得下晶体管通过偏置下栅极而被激活，并且通过偏置上栅极来激活上晶体管。还公开了制造和操作该装置的方法。

50. 发明申请

US20120235214A1 LOCALLY 2 SIDED CHC DRAM ACCESS TRANSISTOR STRUCTURE 有权
标题翻译：本地2个CHC DRAM访问晶体管结构
公开(公告)号：US20120235214A1
公开(公告)日：2012-09-20
申请号：US13047774
申请日：2011-03-14
申请人： Werner Juengling
发明人： Werner Juengling
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10879 , H01L27/10826
摘要： A method for forming a DRAM memory with a two-sided transistor includes: providing a silicon finFET structure having at least two fins, and a trench between the fins; forming high ohmic gates on either side of the fins; forming a hole between each pair of high ohmic gates to enable connection between the pair of high ohmic gates; forming a gate on one side of the trench and underneath one of the pair of high ohmic gate; forming a layer of oxide over the gate; and depositing tungsten in the trench to form a thick layer of metal at the bottom to form a word line.
摘要翻译：用于形成具有双面晶体管的DRAM存储器的方法包括：提供具有至少两个散热片的硅finFET结构和鳍片之间的沟槽; 在翅片的两侧形成高欧姆门; 在每对高欧姆门之间形成一个孔，以使一对高欧姆门之间能够连接; 在沟槽的一侧形成栅极，并在该对高欧姆栅极之一的下面形成栅极; 在门上形成一层氧化物; 并且在沟槽中沉积钨以在底部形成厚的金属层以形成字线。

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